Sang-Seol Lee

Design of a mixed prime factor FFT for portable digital radio mondiale receiver

To achieve better sound quality and to improve data reception, digital radio mondiale (DRM) offers a worldwide initiative to bring analog amplitude modulation (AM) radio into the digital era. DRM systems use coded orthogonal frequency division multiplexing (COFDM) modulation with a multilevel coding scheme to get high resistance to the multipath padding and interference. The bandwidth of a DRM passband signal is less than 20 kHz and the number of carriers used in orthogonal frequency division multiplexing (OFDM) modulation is relatively small. For this reason, DRM systems use non-power-of-two Fast Fourier Transforms (FFT) for OFDM demodulation, such processing gives way to more speed and power consumption in critical paths in DRM receivers. In this paper, we propose a mixed radix-2n and prime factor FFT algorithm for portable DRM receivers. Using the proposed architecture, we can reduce the processing time and energy consumption compared to conventional digital signal processor (DSP) based DRM receivers.

A real-time stereo depth extraction hardware for intelligent home assistant robot

One of the fastest growing next generation consumer products is a robot technology industry and it is rapidly forming a huge market. A depth extraction is one of the key techniques to adopt a home assistant robot for avoiding obstacles and looking for a transfer route. However, a home assistant robot mounted stereo vision systems produce unpredictable changes in video sequences when the robot is walking and needs hard computation to produce an accurate estimation. In this paper, we propose hardware based realtime stereo depth extraction method for an intelligent home assistant robot. For fast adaption of the external environment, we present depth map extraction algorithm by using preprocessing, parallel prediction searching employing median filter. Experimental results show that the proposed method reduces the processing time and the energy consumption compared to the conventional methods. This implementation is suitable for adaptive real-time depth extraction that is compatible with current robot applications.

Narrowband Physical Layer Design for WBAN System

This paper propose the design of PHY simulator for WBAN system in IEEE 802.15.6. Recently, WBAN system is most popular system in wireless communication. According to the technical requirement of the WBAN task group, many companies and research institutes have proposed physical layer architectures to provide fundamental technologies for the WBAN communication systems. Since there are various service scenarios for in-body or on-body applications, the physical layer proposals include UWB as well as narrowband techniques. The implemented WBAN PHY simulator (in this paper) is designed fixed point that is specified PPDU structure and modulation method in WBAN TG6. In the WBAN PHY case, the modulations method is changed by frequency band and data rate. After implementation of simulator, we are going to design WBAN for hardware implementation. We are supposed to implement architecture of a chip that has mixed mode, PSK and FSK in MICS baseband for WBAN. WBAN simulator is designed by using MATLAB.

Implementation of High Efficient CAVLC Encoder for H.264/AVC

This paper proposes the design and VLSI implement of high efficient Context-based Adaptive Variable Length Coding (CAVLC) encoder which adopted a modified Variable Length Coding (VLC) look up table technique and parallel processing. The proposed CAVLC encoder used upper and under buffer as input buffer to perform zigzag scanning with both way ordering. Because of this, the proposed CAVLC encoder can be read and write concurrently. Moreover, we design the CAVLC encoder procedure with parallel processing which uses two generators for information signals and control signals to operate CAVLC modules such as a coeff_token (TotalCeff and TrailingOnes) module, a level module, a total_zeros module, and a run_before module. The proposed CAVLC is prototyped in Verilog-HDL, implemented and synthesized with megnachip 0.18 µm CMOS tech. The synthesis result shows that the gate count is about 12K with the clock constraint of 140Mhz. The proposed CAVLC encoder is suitable for real-time video applications.

An IEEE 802.11g WLAN digital baseband processor using hybrid channel estimation for wireless home A/V receivers

The delivery of digital multimedia data over wireless networks enables many useful consumer applications such as home entertainment. However, there are many performance-related issues associated with the delivery of time-sensitive multimedia content over current wireless communication systems such as those using the IEEE 802.11 standards. Among the most significant issues are the high error rates, because of the media characteristics, and signal attenuation with distance. In this paper, we present a robust digital baseband processor using hybrid channel estimation for wireless home audio-video receivers operating on an IEEE 802.11g wireless local area network (WLAN). The proposed hybrid channel estimation is a combined decision-directed and pilot-assisted method for perfect channel state information (CSI). Experimental results show that the proposed method increases system performance by about 3 dB over the least squares (LS) scheme at 100-ns root mean square (RMS) delay.

Robust JPEG2000 Image Transmission over IEEE 802.15.4

There are so many needs for image transmission through the sensor network. To meet these needs, we propose AUEP(Adaptive Unequal Error Protection) scheme for JPEG2000 image transmission through the IEEE 802.15.4. The AUEP method assign adaptive code rate resulting from PER(Packet Error Rate). The results which are given through the experiments show that the decoding rate and image quality are improved by the proposed adaptive unequal error protection technique.

Prostate cancer classification processor using DNA computing technique

Recently, classification and gene selection of DNA microarray data are important in biomedical research. DNA microarray data provide useful information that can be used to discover the complex mechanism of cancer development. DNA computing techniques are alternative approaches to analyze the DNA microarray data.In this paper, we propose the VLSI implementation of a prostate cancer classification processor. The proposed architecture uses parallel and pipelined processing to improve speed and uses cyclic random masks to reduce memory size. We evaluated the prostate cancer classification processor by testing its performance on prostate cancer microarray data. From the experimental results, the proposed architecture reduced the memory size and classification time with little loss of classification accuracy.

Hardware implementation of fast high dynamic range processor for real-time 4K UHD video

The high dynamic range (HDR) has become very important because of the rapid increase in demand for a variety of applications. However, most of them were implemented by expensive systems due to the high complex computation for processing the real-time 4K UHD video. In the proposed hardware, the non-linear camera response function (CRF) with the area optimization of logarithmic computations has been applied to improve HDR quality. And, for embedding in Field Programmable Gate Array (FPGA), we implement a dedicated hardware using 4006 lookup table (LUT) and 21KB sized internal memory. The proposed architecture enables a real-time HDR processing with pipelining for a UHD video (8 Mega pixels) at 30 frames per second.

Hardware implementation of fast traffic sign recognition for intelligent vehicle system

In intelligent vehicle systems, the traffic sign recognition (TSR) has become very important because of the rapid increase in demand of intelligent transportation system (ITS). However, most of them were implemented by expensive systems due to the high complex computation for processing the real-time segmentation and recognition process. In this paper, the preprocessing with the red region extraction in the RGB color space has been applied to improve TSR performance. To implement proposed architecture, we adopt the Xilinx Virtex-7 V2000T Field Programmable Gate Array (FPGA) with a fully pipelined structure. Experimental results show that the implemented preprocessing block use 1,212 lookup table (LUT) and 11.14 KB sized internal memory. The proposed architecture enables a real-time TSR processing with pipelining for a full-HD (FHD) video (2 Mega pixels) at 60 frames per second.

Memory optimization of bilateral filter and its hardware implementation

As a method for edge-preserving or noise-reducing, a bilateral filter is widely used. However, because every pixel in a filtering window needs a separate Look-Up Table (LUT) for the parallel processing, its hardware implementation is still bulky. In this paper, we propose Similar Weight Grouping (SWG) which maps multiple indexes with a similar value onto a single index and Zero Value Suppression (ZVS) which removes indexes with a value of almost zero to reduce a size of the LUT. By our scheme, a total size of LUT is reduced by approximately 95% while maintaining its performance. Finally, it is implemented using 7.7 KB on-chip memory and 93.1 Kgates with 65 nm process.