Duk-Kyu Park

Fast acquisition frequency synthesizer with the multiple phase detectors

The authors propose a frequency synthesizer which is implemented by deploying a multiple phase detector scheme, and by adding a bias voltage corresponding to desired frequency to the input of a voltage controlled oscillator (VCO) and resetting each divider. One can obtain a fast acquisition time within one cycle of the reference frequency. The acquisition time which is generated by the variation of bias voltage in the VCO due to temperature characteristics can also be minimized by using the proposed multiple phase detectors. The authors have compared the acquisition time of the new frequency synthesizer with a conventional frequency synthesizer and a significant improvement was obtained. The performance was verified by experiments.<<ETX>>

Fast-acquisition PLL synthesizer using a parallel N-stage cycle swallower with low power consumption and low phase noise

A phase-locked loop (PLL) frequency synthesizer with an N-stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers, but the use of the NSCS results in high power consumption and phase noise in the UHF band. This paper elucidates these problems and proposes a fast-acquisition PLL synthesizer using a novel type of NSCS with low power consumption and low phase noise. Experimental results confirm that the use of a parallel NSCS and a prescalar results in greatly reduced power consumption and phase noise. >

Digital phase-locked loop with wide lock-in range using fractional divider

The authors propose a novel type of digital phase-locked loop (DPLL) with both a wide initial lock-in range and a fast initial acquisition time. In this DPLL, by using a fractional divider, it is possible for an initial fixed clock to be made as the adapting free-running frequency which is dependent on the input frequency. Therefore, one can obtain a wide initial lock-in range. Furthermore, removing the frequency offset by a fractional divider and resetting the divider, this system has a fast initial acquisition time of only 16 cycles of input. The properties of the proposed DPLL are investigated by experiments and theoretical analysis, and they are compared with those of the conventional DPLL. The results show that the proposed DPLL performs well.<<ETX>>

Fast acquisition PLL frequency synthesizer with improved N-stage cycle swallower

A new type of fast acquisition frequency synthesizer which improves the operation of the NSCS (N-stage cycle swallower) is proposed. By varying the output frequency of the NSCS and by adopting a programmable divider, the proposed synthesizer has an output frequency of deviation within 0.0003 ppm. By introducing an extra switching operation of the last stage division ratio in the NSCS, the proposed synthesizer can have an extremely fast acquisition time.<<ETX>>

Fast acquisition PLL synthesizer using parallel N-stage cycle swallower (NSCS)

A phase-locked loop (PLL) frequency synthesizer with an N-stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers, but the use of the NSCS results in high power consumption and phase noise in the UHF band. This paper elucidates these problems and proposes a fast-acquisition PLL synthesizer using a novel type of NSCS with low power consumption and low phase noise. Experimental results confirm that the use of a parallel NSCS and a prescalar results in greatly reduced power consumption and phase noise.<<ETX>>

Improved performance of fast acquisition PLL synthesizer with N‐stage cycle swallower

The PLL frequency synthesizer with an N-stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers. The synthesizer, however, requires many stages in the NSCS to obtain accurate output frequencies. In this paper, to obtain both more accurate output frequencies with a few stages and a higher speed acquisition time, we propose two methods for improving NSCS switching operation. First, by allowing the NSCS output frequency to be variable a large range of choices in the division ratios becomes available in the NSCS. The proposed synthesizer has the output frequency of deviation within 0.0003 ppm when the 3-stage cycle swallower is employed. Second, by temporarily increasing the expected amount of the variation in the output frequency, the acquisition time of the NSCS synthesizer can be improved. Experimental results confirm that the proposed technique results in a shortened acquisition time.

A modified time-shared code tracking loop for frequency hopping systems

A modified time-shared code tracking loop (MTSL) for frequency-hopped signals is presented. The tracking performance of the MTSL in the presence of white Gaussian noise is analyzed. An analytical expression for the code tracking jitter performance is derived and plotted, and the results compared to those obtained for the traditional time-shared loop (TTSL) and the traditional full-time loop (TFTL). Results show that the MTSL obtains a code tracking jitter less than those of the TTSL and the TPTL for given S/N.