E. Cartier

Passivation and interface state density of SiO2/HfO2-based/polycrystalline-Si gate stacks

We demonstrate that a forming gas annealing temperature of 520u200a°C significantly improves interface state passivation for SiO2/HfO2-based/polycrystalline-Si gate stacks as compared to annealing at 420u200a°C normally used for SiO2/polycrystalline-Si gate stacks. We also show that the initial interface state density is dependent upon the interfacial SiO2 preparation, whereby a chemically grown oxide has a higher initial interface state density as compared to a thermally grown oxide.

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.

Effect of bulk trap density on HfO/sub 2/ reliability and yield

The trap density in an ALD SiO/sub 2//HfO/sub 2/ stack is measured with charge pumping. A critical trap density at breakdown is found and a percolation model is proposed to explain HfO/sub 2/ breakdown. On this particular stack, a direct link between the bulk trap density and the HfO/sub 2/ yield and reliability is demonstrated. A low initial HfO/sub 2/ bulk trap density is essential in order to guarantee the reliability of these stacks.

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

HfO/sub 2/ nMOSFETs and pMOSFETs were fabricated using scaled chemical oxides as a starting interface, together with sputtered (PVD) TiN gate electrodes. Aggressively scaled stacks of 8.2 /spl Aring/ EOT on nMOS and 7.5 /spl Aring/ EOT on pMOS were achieved with leakage current of <5 A/cm/sup 2/ at V/sub FB/ +1 volts. Low fixed charge density in the HfO/sub 2/ layer was observed from VFB extraction, using high frequency-CV measurements, when considering a TiN workfunction of 4.78 eV. Conventional C-V hysteresis and transient V/sub T/ instability measurements on sub 1 nm TiN/HfO/sub 2/ devices indicated reduced instability as a result of EOT scaling. The electron mobility is degraded with EOT scaling whereas hole mobility remains constant down to an EOT of 8 /spl Aring/.

Electrical characterisation of high-k materials prepared by atomic layer CVD

The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO/sub 2/ as the gate dielectric. Replacement of SiO/sub 2/ with a high dielectric constant material allows an increase in the physical oxide thickness, while maintaining a low equivalent oxide thickness (EOT) and low direct tunnelling current. The high-k gate dielectric of choice will most likely be a deposited film, which makes the replacement of SiO/sub 2/, a thermally grown layer, even more challenging. Atomic layer CVD (ALCVD/sup TM/) is a well-controlled surface saturating process using gas-solid interactions to deposit thin films. The technique results in covalent bonding between the gaseous precursors and the surface bonding sites. ALCVD/sup TM/ provides highly uniform layers and the possibility to deposit many materials, including mixed oxide layers and nano-laminates. Some of the challenges facing high-k materials include achieving a high quality Si/high-k interface, film stability and solving reliability and integration issues. In this paper, we use MOS capacitors to investigate these challenges for Al/sub 2/O/sub 3/-TiN and Al/sub 2/O/sub 3/-ZrO/sub 2/-TiN gate stacks.

Thermal stability and scalability of Zr-aluminate-based high-k gate stacks

It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.

Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained. Sputtered TiN gate on the identical stacks yielded 0.82 nm EOT on NMOS devices using scaled chemical oxide interface with leakage current of 10/sup -3/ A/cm/sup -2/. CV hysteresis of TiN/HfO/sub 2/ was observed to decrease by an order of magnitude from the as deposited value to <10 mV after a 900/spl deg/C N/sub 2/ anneal.

Scaling of high-k dielectrics towards sub-1nm EOT

High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperature stability. Various surface preparation methods and deposition conditions are tested. Compatibility of the high-k stacks with poly-Si and metal electrodes is investigated. Significant improvements in yield and thermal stability are obtained by optimized modifications of the high-k stack. Scaling of the equivalent oxide thickness (EOT) is accomplished by implementing novel ideas in interface engineering and high-k materials processing. High-k stacks are tested in transistor structures with small gate lengths. The origin of the electrical instabilities and the observed drive current degradation of high-k transistors as compared to the SiO/sub 2/ reference transistors are studied in detail.

Strong correlation between dielectric reliability and charge trapping in SiO/sub 2//Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

Polarity-dependent charge trapping and defect generation have been observed in SiO/sub 2//Al/sub 2/O/sub 3/ gate stacks with TiN electrodes. For the substrate injection case, electron trapping in the bulk of the Al/sub 2/O/sub 3/ films dominates, whereas hole trap near the Si substrate is observed for gate injection. This asymmetry in defect creation causes an asymmetry in oxide reliability. For gate injection, reliability is limited by the thin SiO/sub 2/ interfacial layer, yielding low beta values, independent of the Al/sub 2/O/sub 3/ thickness. For substrate injection, reliability is limited by electron trap generation in the bulk of the Al/sub 2/O/sub 3/ film, yielding a strong thickness dependence of the beta values, as expected from the percolation model and as observed in SiO/sub 2/ layers of similar thickness.