G. Groeseneken

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

SILC-related effects in flash E/sup 2/PROM's-Part I: A quantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO/sub 2/ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism.

New interface state density extraction method applicable to peaked and high-density distributions for Ge MOSFET development

A method for extracting parameters of weakly Fermi-level pinned germanium (Ge) capacitors is introduced. This method makes progress toward a more generally valid reliable interface state parameter extraction. Such a general method is needed to evaluate and explain the behavior of Ge MOS capacitors, which show characteristics deviating considerably from silicon. The encountered weak pinning confirmed by the new extraction method explains the degraded Ge nMOSFET performance.

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

Hot hole degradation effects in lateral nDMOS transistors

The degradation of a n-type lateral DMOS transistor is shown to be related to the injection of hot holes in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. The dependency of the hot hole injection on the layout of the LDMOS transistors is studied.

Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress

By means of leakage current measurements, charge pumping and TDDB analysis, we construct a consistent model for the degradation and breakdown of 0.9 nm EOT atomic layer deposited (ALD) HfO2. During degradation, traps and two-trap clusters are formed in the HfO 2 giving rise to considerable SILC. The two-trap clusters subsequently wear out, finally leading to an abrupt hard breakdown. We demonstrate that 0.9 nm EOT ALD HfO2 is intrinsically reliable under constant voltage stress if hard breakdown is used as a failure criterion

Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing

The triggering of grounded gate nMOSFET (gg-nMOS) and field-oxide devices (FOXFETs), essential for optimized ESD protection design, is addressed by TLP-pulsed emission microscopy. Current nonuniformity and instability effects in snapback operation under DC and TLP conditions are demonstrated. The comprehensive correlation of emission and electrical behaviour allows an improved interpretation of device operation. Technological influences on the trigger uniformity are discussed.

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

Hot-carrier degradation in submicrometre MOSFETs: from uniform injection towards the real operating conditions

An overview is given of the present understanding of the hot carrier degradation problem in submicrometre MOSFETs. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behaviour under the most relevant case for real operation, namely dynamic degradation. Finally, the strategies for improving hot carrier reliability and a forecast of the hot carrier reliability problem for sub-0.25 mu m technologies are briefly discussed.

Stress-Induced Positive Charge in Hf-Based Gate Dielectrics: Impact on Device Performance and a Framework for the Defect

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability Delta Vth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates Delta Vth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of Delta Vth is clarified.