E. De Backer

I3T80: a 0.35 /spl mu/m based system-on-chip technology for 42 V battery automotive applications

This paper introduces a new modular 0.35 /spl mu/m based smart power technology which is compatible with the new 42 V battery automotive standard. The I3T80 technology offers various types of DMOS transistors in the range between 15 to 80 V. A set of bipolars, a high voltage floating diode, a large array of passive components, floating logic up to 80 V and 4 kV HBM compatible ESD protection structures are available. In addition, embedded flash memory is offered.

Plasma-charging damage of floating MIM capacitors

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors. Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates. New design rules are proposed in order to predict and automatically flag possible PCD sites. Furthermore, layout solutions to reduce PCD are suggested.

MIMC reliability and electrical behavior defined by a physical layer property of the dielectric

Metal-insulator-metal capacitor (MIMC) reliability and electrical properties are defined by the TDDB lifetime. breakdown voltage and leakage current. In this article, the correlation is determined between these electrical properties and the physical and chemical properties of the SiN dielectric layer. It is demonstrated how a SiN dielectrics with a high refractive index have high Si content and show an increased initial leakage Current. However, contradictory to the high leakage current, these dielectrics also show high lifetimes. It is shown that SiN dielectrics with a high Si content contain high numbers of charge trapping centers. Over time, a high concentration of trapped charges is build up to such an extend that the local electric field over the dielectric is significantly decreased. This results in the observed reliability improvement of the dielectric. The final intrinsic quality and reliability of MIMC capacitors can therefore be determined by Measurable physical properties of the MIMC dielectric at the time of the deposition of this layer

Non Contact Surface Potential Measurements for Charging Reduction During Manufacturing of Metal-Insulator-Metal Capacitors

In this paper, charging induced damage (CID) to metal-insulator-metal-capacitator (MIMC), is reported. The damage is caused by the build up of charges on an oxide surface during a water rinsing step. The excessive charging over a large capacitator area results in a discharge over the inter metal dielectric layer (IMD) towards a grounded structure. This CID leads to direct severe yield loss. The charging has been detected, measured and reduced with the help of a non contact surface potential measurement.In this way further yield losses have been prevented. A modelfor the relation between the surface charging potential and the voltage difference between the capacitator and the grounded structure is presented.

Water-Assisted Positive Ion Contamination Resulting in Charge Loss in Nonvolatile Memories

In this paper, the influence of back-end processing on the charge retention of floating gate nonvolatile memories is extensively studied. By implementing a wide variety of options for the back-end architecture, a consistent picture of the charge loss mechanisms is obtained, proving the dominant role of water assisted positive ion contamination and the blocking capability of the SiN passivation layer.

Improvement of non volatile memory tunnel oxide robustness and integrity by design optimization of the memory cell

During the processing of CMOS with embedded NVM, an issue with the tunnel oxide was discovered. On part of the wafer, the tunnel oxide was very leaky and had a charge to breakdown (QBD) that was close to zero. The sensitivity of a capacitor test structure towards degradation due to the cleaning prior to the oxidation is depending very much on the design of the test structure. A very strong impact of the isolation of the test structure is observed. Gate oxide grown on a P-type well, that is electrically isolated by multiple junctions from exposed N-type well, was found to be very sensitive to Si surface cleaning treatment prior to the oxidation. When both P-type and N-type Si with only a single junction in between are exposed during this cleaning, then the oxide grown in the P-type silicon becomes very robust and insensitive to the surface treatment prior to the oxidation. Evidence is brought that the improvement of this P-type Si is due to the occurrence of an electrolytic cell in the Si during the cleaning. The electrolytic cell is formed by the exposed N- and P-type regions as electrodes and the cleaning chemicals as electrolyte. In this cell, the exposed N-type region is protecting the exposed P-type region against degradation of the Si surface during this cleaning treatment prior to the tunnel oxidation. As far as we know, for the first time it is demonstrated that with the proper design of connected N-type and P-well regions, it is possible to establish a very robust tunnel oxide in a P-type well that is insensitive to process variations during the cleaning of Si prior to the tunnel oxidation.

Plasma damage in HIMOS/spl trade/ non-volatile memories (NVM)

In this paper, for the first time, plasma induced damage (PID) on floating gate based non-volatile memory cells is reported. Since the cells consist of a complex combination of tunnel and gate oxides, combined with a dense frame of metal interconnect, the chance that these cells may be affected by plasma damage is evident. In order to investigate if the plasma damage affects the flash memory cells, the appropriate test structures have been designed, manufactured and measured. The test structures include structures to generate plasma damage as well as possible protective structures to prevent plasma damage.

Plasma charging damage reduction in IC processing by a self-balancing interconnect

A small TPC has been read out by means of a Medipix2 chip as direct anode. A Micromegas foil was placed Click to view the MathML source above the chip, and electron multiplication occurred in the gap. With a He/isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90%. With this new readout technology for gas-filled detectors we recorded many image frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as ?-rays. With a gas layer thickness of only 1 mm, the device could be applied as vertex detector, outperforming all Si-based detectors.

Use of Oxynitride Dielectric to Maximise the Growth Rate of Selective Epitaxial Base Layer in a Self-Aligned Double-Polysilicon SiGe Bipolar Transistors

State of the art SiGe BiCMOS processed with a double-polysilicon self-aligned Heterojunction Bipolar Transistor (HBT) is fabricated by means of selective epitaxial deposition. Typically the deposition rate of the epitaxial layer is kept very low to ensure the selectivity. This is having a negative impact on manufacturability and cost. The paper is describing the development, properties and use of a new oxynitride interpoly layer that allows an improvement of growth rate of the selective epitaxial layer by a factor 4 to 5. This development is implemented in an industrial 0.35 µm SiGe BiCMOS technology [1].

An industrial 0.35 /spl mu/m SiGe BiCMOS technology for 5 GHz WLAN featuring an improved selective epitaxial growth process

A SiGe BiCMOS process with a double-polysilicon self-aligned Heterojunction Bipolar Transistor (HBT) fabricated by means of selective epitaxy has been developed. The selective epitaxial growth is improved with the use of an innovative oxy-nitride interpoly layer which increases the growth rate. The HBT features a current gain cut-off frequency f/sub T/ of 43 GHz and a maximum available cut-off frequency f/sub MAX/ of 80 GHz at a collector-emitter bias voltage of 3 V. N-p-n transistors are integrated in 0.35 /spl mu/m CMOS process with high quality RF passive components. A Low Noise Amplifier (LNA) designed in this technology for 5 GHz wireless local area networks (WLAN) demonstrated measurement data close to the simulated ones.