M. Tack

A novel hot-hole injection degradation model for lateral nDMOS transistors

For the first time, the degradation of a DMOS transistor is shown to be due to hot hole injection in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. A very good agreement with experimental data is obtained for various stressing conditions.

A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors

This paper presents a comprehensive yet physical model for hot carrier degradation in LDMOS transistors. The only model input parameters are the gate and drain voltage Vds and Vgs , the internal device temperature and the device width W. The model allows calculating AC degradation performance out of the DC hot carrier data. A physical explanation of the observed effects is provided, and important differences between LDMOS and standard CMOS are highlighted

I3T80: a 0.35 /spl mu/m based system-on-chip technology for 42 V battery automotive applications

This paper introduces a new modular 0.35 /spl mu/m based smart power technology which is compatible with the new 42 V battery automotive standard. The I3T80 technology offers various types of DMOS transistors in the range between 15 to 80 V. A set of bipolars, a high voltage floating diode, a large array of passive components, floating logic up to 80 V and 4 kV HBM compatible ESD protection structures are available. In addition, embedded flash memory is offered.

Development of a robust 50V 0.35 /spl mu/m based Smart Power Technology using trench isolation

This paper describes a new 0.35 /spl mu/m CMOS based smart power technology. The so-called I3T50 technology belongs to a series of intelligent interface technologies developed within AMI Semiconductor over the past years. This technology is suitable for applications up to 50 V, such as automotive, peripheral and consumer applications. Trench isolation is used to isolate the devices, substantially reducing the isolation area. The set of devices available within this technology consists of n-type and p-type CMOS and DMOS devices, bipolar transistors, a high voltage floating diode, passive components, OTP memory and a set of ESD protection structures. In the future, the technology will be extended also with a modular embedded flash memory.

XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit

Record performance of a novel power transistor integrated in a 0.35 μm power IC technology is reported. Measured specific on-state resistance of 33 mOhm*mm2 for a 94 V breakdown is breaking the silicon-limit and is the lowest reported value to date. The device outperforms its nearest rival by a factor of 2.5. The device consists of the stacking of a vertical MOS on a fully depleted vertical drift layer, leading to a high cell density

Electron trapping and interface trap generation in drain extended PMOS transistors

The hot carrier behavior of a p-type lateral drain extended MOS (DeMOS) is for the first time investigated using charge pumping (CP). In an early stage of hot carrier stress, electron injection and trapping occurs. With increasing stress time, the interface trap formation in the spacer oxide becomes the dominant mechanism. In this way, the abnormal degradation of the specific on-resistance Ron is explained.

Plasma-charging damage of floating MIM capacitors

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors. Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates. New design rules are proposed in order to predict and automatically flag possible PCD sites. Furthermore, layout solutions to reduce PCD are suggested.

Dynamics of integrated vertical DMOS transistors under 100-ns TLP stress

On-wafer transmission line pulsing (TLP) measurements and transient interferometric mapping experiments on vertically integrated DMOS transistors reveal the presence of hot filament hopping between the two parasitic bipolars. The activity of both intrinsic bipolar transistors is dependent on the TLP current. In addition, a traveling filament along the device width is observed, the traveling speed being estimated to be between 370 and 480 m/s.

Reliability assessment of deep trench isolation structures

An extensive investigation of the reliability of deep trench isolation structures upon reverse bias stress is performed. By using the variable base level charge pumping technique, it is shown that the degradation of the trench primarily originates from N/sub it/ formation at the inner trench corners. The reliability is improved by introducing cut corners.

Theoretical analysis of XtreMOS ™ power transistors

This work provides a new theoretical approach addressed to the XtreMOSTM and equivalent structures. An analytical sRonxBVdss model is provided to demonstrate the superior electrical performance of XtreMOSTM structure in the domain of the high power MOSFETs at medium voltage capability (50-200 V). Moreover, geometrical and technological parameters can be easily optimized by means of simple expressions. In order to support and validate the theoretical approach, numerical simulation and experimental data are included.