J. Ackaert

Plasma-charging damage of floating MIM capacitors

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors. Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates. New design rules are proposed in order to predict and automatically flag possible PCD sites. Furthermore, layout solutions to reduce PCD are suggested.

Impact of reactor- and transistor-type on electron shading effects

Electron shading (ES) effects, which lead to plasma process-induced damage in etching processes, were studied as a function of reactor- and transistor-type. It was found that the classical ES effect, which occurs under the latent antenna regime, dominates for the current high-density plasma reactors, independent of the used transistor-type. However, for less dense plasma reactors, the so-called extended ES effect, which occurs during the overetch regime, can overrule the classical ES effect depending on the transistor-type.

MIMC reliability and electrical behavior defined by a physical layer property of the dielectric

Metal-insulator-metal capacitor (MIMC) reliability and electrical properties are defined by the TDDB lifetime. breakdown voltage and leakage current. In this article, the correlation is determined between these electrical properties and the physical and chemical properties of the SiN dielectric layer. It is demonstrated how a SiN dielectrics with a high refractive index have high Si content and show an increased initial leakage Current. However, contradictory to the high leakage current, these dielectrics also show high lifetimes. It is shown that SiN dielectrics with a high Si content contain high numbers of charge trapping centers. Over time, a high concentration of trapped charges is build up to such an extend that the local electric field over the dielectric is significantly decreased. This results in the observed reliability improvement of the dielectric. The final intrinsic quality and reliability of MIMC capacitors can therefore be determined by Measurable physical properties of the MIMC dielectric at the time of the deposition of this layer

Prevention of plasma induced damage on thin gate oxide of HDP oxide deposition, metal etch, Ar preclean processing in BEOL sub-half micron CMOS processing

In this paper a comparison is made of several PID measurement techniques. A novel mechanism of plasma induced damage (PID) by high density plasma (HDP) inter metal dielectric (IMD) deposition is proposed. Results of a design of experiment (DOE) on Ar preclean minimizing PID are presented. For metal etch, HDP etch is compared reactive ion etch and the impact of individual process steps are identified by specialized antenna structures. Measurement results of Charge Pumping (CP), breakdown voltage (V/sub bd/) and gate oxide leakage are correlating very well. For HDP oxide deposition, plasma damage is minimal, assuring minimal exposure time of the metal line to the plasma using maximal deposition to sputter ratio. This process is inducing less PID than the classic SOG processing. Ar preclean induces minimal plasma damage using minimal process time, high ion energy and high plasma power. On metal etch, reactive ion etch is inducing less plasma damage then HDP etching. For both reactors PID is induced only in the metal over etch step.

Correlation between hot carrier stress, oxide breakdown and gate leakage current for monitoring plasma processing induced damage on gate oxide

In this paper, we compare the HC stress and oxide breakdown results with the fast and commonly used gate leakage current measurement A clear correlation is found between low levels of gate leakage and both HC degradation and oxide breakdown. We, for the first time, demonstrate that the value of the gate leakage current is not only a failure indicator in the region about 1 nA but also a good indicator of the reliability of the devices in the region between 1 pA and 1 nA. Thus, from the value of gate leakage current one can estimate the reliability of the devices, saving precious measurement time.

Non Contact Surface Potential Measurements for Charging Reduction During Manufacturing of Metal-Insulator-Metal Capacitors

In this paper, charging induced damage (CID) to metal-insulator-metal-capacitator (MIMC), is reported. The damage is caused by the build up of charges on an oxide surface during a water rinsing step. The excessive charging over a large capacitator area results in a discharge over the inter metal dielectric layer (IMD) towards a grounded structure. This CID leads to direct severe yield loss. The charging has been detected, measured and reduced with the help of a non contact surface potential measurement.In this way further yield losses have been prevented. A modelfor the relation between the surface charging potential and the voltage difference between the capacitator and the grounded structure is presented.

Improvement of non volatile memory tunnel oxide robustness and integrity by design optimization of the memory cell

During the processing of CMOS with embedded NVM, an issue with the tunnel oxide was discovered. On part of the wafer, the tunnel oxide was very leaky and had a charge to breakdown (QBD) that was close to zero. The sensitivity of a capacitor test structure towards degradation due to the cleaning prior to the oxidation is depending very much on the design of the test structure. A very strong impact of the isolation of the test structure is observed. Gate oxide grown on a P-type well, that is electrically isolated by multiple junctions from exposed N-type well, was found to be very sensitive to Si surface cleaning treatment prior to the oxidation. When both P-type and N-type Si with only a single junction in between are exposed during this cleaning, then the oxide grown in the P-type silicon becomes very robust and insensitive to the surface treatment prior to the oxidation. Evidence is brought that the improvement of this P-type Si is due to the occurrence of an electrolytic cell in the Si during the cleaning. The electrolytic cell is formed by the exposed N- and P-type regions as electrodes and the cleaning chemicals as electrolyte. In this cell, the exposed N-type region is protecting the exposed P-type region against degradation of the Si surface during this cleaning treatment prior to the tunnel oxidation. As far as we know, for the first time it is demonstrated that with the proper design of connected N-type and P-well regions, it is possible to establish a very robust tunnel oxide in a P-type well that is insensitive to process variations during the cleaning of Si prior to the tunnel oxidation.

Plasma damage in HIMOS/spl trade/ non-volatile memories (NVM)

In this paper, for the first time, plasma induced damage (PID) on floating gate based non-volatile memory cells is reported. Since the cells consist of a complex combination of tunnel and gate oxides, combined with a dense frame of metal interconnect, the chance that these cells may be affected by plasma damage is evident. In order to investigate if the plasma damage affects the flash memory cells, the appropriate test structures have been designed, manufactured and measured. The test structures include structures to generate plasma damage as well as possible protective structures to prevent plasma damage.

Plasma charging damage reduction in IC processing by a self-balancing interconnect

A small TPC has been read out by means of a Medipix2 chip as direct anode. A Micromegas foil was placed Click to view the MathML source above the chip, and electron multiplication occurred in the gap. With a He/isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90%. With this new readout technology for gas-filled detectors we recorded many image frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as ?-rays. With a gas layer thickness of only 1 mm, the device could be applied as vertex detector, outperforming all Si-based detectors.

Use of Oxynitride Dielectric to Maximise the Growth Rate of Selective Epitaxial Base Layer in a Self-Aligned Double-Polysilicon SiGe Bipolar Transistors

State of the art SiGe BiCMOS processed with a double-polysilicon self-aligned Heterojunction Bipolar Transistor (HBT) is fabricated by means of selective epitaxial deposition. Typically the deposition rate of the epitaxial layer is kept very low to ensure the selectivity. This is having a negative impact on manufacturability and cost. The paper is describing the development, properties and use of a new oxynitride interpoly layer that allows an improvement of growth rate of the selective epitaxial layer by a factor 4 to 5. This development is implemented in an industrial 0.35 µm SiGe BiCMOS technology [1].