E. de la Torre

Design methodologies based on hardware description languages

In this paper, we are presenting the basic methodology to be used in the design of a digital system, based on the use of hardware description languages. The most important stages of the design flow and the computer-aided design tools involved are presented, from the initial specification to the final implementation. The design flow described in the paper is based on a top-down approach, as this is the methodology currently used for most of the digital systems to face the current system complexity. Although all the concepts and methods are feasible for any kind of digital electronic system, application-specific integrated circuits are, in particular, considered as an application example in the paper. Most of the examples shown are written in VHSIC HDL, as it is an IEEE Standard and is one of the most commonly used.

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors

Specific features of Wireless Sensor Networks (WSNs) like the open accessibility to nodes, or the easy observability of radio communications, lead to severe security challenges. The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate. In order to avoid dependencies on a compromised level of security, a WSN node with a microcontroller and a Field Programmable Gate Array (FPGA) is used along this work to implement a state-of-the art solution based on ECC (Elliptic Curve Cryptography). In this paper it is described how the reconfiguration possibilities of the system can be used to adapt ECC parameters in order to increase or reduce the security level depending on the application scenario or the energy budget. Two setups have been created to compare the software- and hardware-supported approaches. According to the results, the FPGA-based ECC implementation requires three orders of magnitude less energy, compared with a low power microcontroller implementation, even considering the power consumption overhead introduced by the hardware reconfiguration.

A Fast Emulation-Based NoC Prototyping Framework

This paper presents an FPGA emulation-based fast network on chip (NoC) prototyping framework, called dynamic reconfigurable NoC (DRNoC) emulation platform. The main, distinguishing, characteristic of this approach is that design exploration does not requires re-synthesis, accelerating the process. For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied. The paper describes all the building elements of the proposed solution: the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system. Results and a use case are shown.

Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs

Virtex II FPGAs are widely used in current designs because of their high density of logic cells and the availability of embedded DSP specific blocks (Multipliers) and Dual port RAMs along with the possibility of dynamic reconfiguration. Systems containing FPGAs could be updated once deployed by loading new configurations received, i.e., via a network connection. Unlike other approaches, which rely on more regular devices, i.e. the older Virtex FPGAs, this paper presents a solution for dynamic core insertion and reallocation that permits cores to make use of the embedded blocks available in Virtex II devices. An application called BITPOS is proposed. It extracts and reallocates Virtex II cores. It is compared with other similar solutions and a survey of existing core generation tools is presented. A feasible slot based architecture with a bus communication structure for reallocatable cores communication has been selected and applied in a prototype demonstrator.

Remote HW-SW reconfigurable Wireless Sensor nodes

Reconfigurable HW, like FPGAs, can improve the processing systems performance as it has been demonstrated by several research groups. Usually, the inclusion of such elements in HW platforms for Wireless Sensor Networks (WSNs) has been rejected by designers, mainly due to the power consumption penalization. A reconfigurable device allows not only performance improvement but also remote HW reconfiguration of the WSN node. In this paper, a entire working flow for generate, remotely configure and reconfigure the HW in a target custom reconfigurable platform developed at CEI (Centro de Electronica Industrial) is presented. The custom platform includes a microprocessor and an FPGA (Xilinx partially reconfigurable) to carry out all the processing tasks. The current reconfiguration process works with the JTAG interface, which makes the solution portable to other FPGAs, especially those new less power consuming devices that are appearing in the market nowadays.

Teaching embedded systems and microcontrollers using scale models

One of the main problems that appear in teaching subjects like embedded systems and microcontrollers is to adequate the theoretical and practical lessons. In this paper we present a teaching experience based on scale models of real systems. The main advantage of the teaching method is the combination of theoretical concepts and practical application of all the concepts learnt at the lectures, using a real system. In this case we have developed two scale models: a garage and a washing car system. The prototypes have been built using Fischer-Technik and contain different electromechanical systems, sensors and actuators, all of them controlled from a 68HC11 board. The experience has been run on two different subjects with a total of 27 students at UPM and the results were extremely good, in terms of concepts learnt and in terms of student satisfaction.

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Systems relying on fixed hardware components with a static level of parallelism can suffer from an under use of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macro block (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly.

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.

Nonintrusive debugging using the JTAG interface of FPGA-based prototypes

The IEEE Std. 1149.1, also known as JTAG, defines a serial interface to access test-dedicated logic embedded in integrated circuits, although it is also being used as an FPGA programming interface. This paper makes an analysis of the possibilities of reusing this infrastructure in debugging applications implemented in FPGAs while in the prototype validation phase, with emphasis on nonintrusive methods. Commercially available FPGAs may offer from basic JTAG implementations, to complex ones. Depending on these features, the paper discusses different methods for monitoring, tracing, debugging and profiling the execution of programs running on a microprocessor. Some of these methods require ad-hoc modules to be inserted, like embedded in-circuit emulators or trace-capable blocks. A tool is presented that demonstrates the possibility of automatically inserting and connecting debug-oriented blocks, and controlling them through the JTAG interface. Application examples are provided, showing the results of the use of the tool with some industrial and academic microprocessor system implementations.