Y. Torroja

Design methodologies based on hardware description languages

In this paper, we are presenting the basic methodology to be used in the design of a digital system, based on the use of hardware description languages. The most important stages of the design flow and the computer-aided design tools involved are presented, from the initial specification to the final implementation. The design flow described in the paper is based on a top-down approach, as this is the methodology currently used for most of the digital systems to face the current system complexity. Although all the concepts and methods are feasible for any kind of digital electronic system, application-specific integrated circuits are, in particular, considered as an application example in the paper. Most of the examples shown are written in VHSIC HDL, as it is an IEEE Standard and is one of the most commonly used.

Teaching embedded systems and microcontrollers using scale models

One of the main problems that appear in teaching subjects like embedded systems and microcontrollers is to adequate the theoretical and practical lessons. In this paper we present a teaching experience based on scale models of real systems. The main advantage of the teaching method is the combination of theoretical concepts and practical application of all the concepts learnt at the lectures, using a real system. In this case we have developed two scale models: a garage and a washing car system. The prototypes have been built using Fischer-Technik and contain different electromechanical systems, sensors and actuators, all of them controlled from a 68HC11 board. The experience has been run on two different subjects with a total of 27 students at UPM and the results were extremely good, in terms of concepts learnt and in terms of student satisfaction.

Nonintrusive debugging using the JTAG interface of FPGA-based prototypes

The IEEE Std. 1149.1, also known as JTAG, defines a serial interface to access test-dedicated logic embedded in integrated circuits, although it is also being used as an FPGA programming interface. This paper makes an analysis of the possibilities of reusing this infrastructure in debugging applications implemented in FPGAs while in the prototype validation phase, with emphasis on nonintrusive methods. Commercially available FPGAs may offer from basic JTAG implementations, to complex ones. Depending on these features, the paper discusses different methods for monitoring, tracing, debugging and profiling the execution of programs running on a microprocessor. Some of these methods require ad-hoc modules to be inserted, like embedded in-circuit emulators or trace-capable blocks. A tool is presented that demonstrates the possibility of automatically inserting and connecting debug-oriented blocks, and controlling them through the JTAG interface. Application examples are provided, showing the results of the use of the tool with some industrial and academic microprocessor system implementations.

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size.

Custom hardware IEEE 1451.2 implementation for smart transducers

The heterogeneity of sensor interfaces has caused the creation of the IEEE 1451.2 standard. This standard proposes a common digital interface for all sensors and a set of instructions to communicate with them. Following this standard, smart networked sensors can become a reality. In addition to the interface functions, an electronic data sheet is included for sensor self-identification in order to ease the process of including new sensors in a network. This work proposes a custom hardware implementation of this standard using a hardware description language, different from the most common implementations based on microcontrollers. The main advantages are full scalability and configurability, technology independence and ease of integration in larger systems.

Design of a CAN interface for custom circuits

This paper presents the experience of the development of a CAN interface to be integrated in custom circuits (ASICs, FPGAs). The CAN controller has been designed in VHDL, so it can be targeted to different implementation technologies. The design method of the block is also presented in the paper as an experience of how to easily design digital systems to be reused in different applications, assuring its quality and reliability.

Exploiting VHDL-RTL features to reduce the complexity of power estimation in combinational circuits

A probabilistic method to calculate signal probabilities in order to estimate the power consumption of VHDL-RTL designs is presented. The propagation of signal probabilities is performed through the extraction of the BDD (Binary Decision Diagram) of the combinational logic. The method exploits some advantages of RTL (Register Transfer Level) designs which leads to smaller BDDs, avoiding the memory explosion caused by the signal dependences. The method is integrated in a design environment to help designers improve the quality and early explore their circuits.

Quality estimation of test vectors and functional validation procedures based on fault and error models

This paper presents a method to estimate the quality of a set of test vectors and the validation procedures from pre-synthesised descriptions in VHDL. The method is based on the definition of fault models, for test features evaluation, and error models, for quality validation estimation.

A comparative analysis of different fault simulation techniques for VLSI circuits testing

Two solutions for the problem of fault simulation of digital integrated circuits and a comparison of their performance are presented. The first fault simulator is a serial simulator. Because of the efficiency of the logic simulation algorithm the results are quite good. The second is a differential fault simulator which takes advantage of the order in which the faults are simulated. These fault simulators will work in an automatic test pattern generation (ATPG) system which deals with combinatorial or sequential scan designed circuits considering the stuck-at-0, 1 fault model. An overview of ATPG systems and different methodologies used in fault simulation is also presented. In the description of the suggested approach, special emphasis is given to the basic logic simulator used to implement the fault simulators. Benchmarks have been developed on ISCAS circuits and were obtained in terms of CPU time, fault coverage and number of events, for a set of random vectors.<<ETX>>

Ardid: A Tool and a Model for the Quality Analysis of VHDL Based Designs

The quality of a product, i.e. a digital design, is a fuzzy concept that can be considered from different points of view. Usually, the most accepted definition of quality is the fulfilment of explicit or implicit requirements. Although there are several definitions of quality ([Cros79] [Demi86] [ISO87]), “quality can not be well defined, but it can, and should be modelled” [Jozw96] .