E. Er

Formation of cobalt silicide spikes in 0.18 μm complementary metal oxide semiconductor process

Co silicide spikes have been found in active contact salicidation in complementary metal oxide semiconductor devices during failure analysis by means of transmission electron microscopy examination. Scanning transmission electron microscopy, energy dispersive x-ray analysis and microdiffraction study revealed that these spikes are CoSi2 with an epitaxial relationship with Si of (111)CoSi2//(111)Si and [110]CoSi2//[110]Si. The formation of the CoSi2 spikes are suspected to be due to the presence of undesired SiOx residue between Co film and Si substrate which acts as a solid diffusion membrane to cause the Si rich phase CoSi2 to precipitate directly inside Si lattice.

Failure analysis of bond pad metal peeling using FIB and AFM

Aluminum bond pads on semiconductor chips play an important role in chips functionality and reliability. Bond pad peeling during wire bonding process results in yield reduction. The failure mechanisms of the peeling must be identified so that potential reliability problem of poor bond pad adhesion can be avoided. In this work, FIB, SEM, EDX, and AFM are used to identify the root causes of the peeling. The possible root causes are found to be the presence of an extra layer of thickness of 0.14 μm and the poly-silicon surface roughness asperity due to prolonged BOE etching time.

Development of a rapid and automated TEM sample preparation method in semiconductor failure analysis and the study of the relevant TEM artifact

Abstract Automated TEM sample preparation using focused ion beam (FIB) followed by plucking has been proposed to be a fast and reliable method in semiconductor failure analysis with extremely short cycle time needs. Artifacts caused by sample supporting film to image quality, energy dispersive X-ray (EDX) and electron energy loss spectrum (EELS) analysis are discussed. Damage (amorphizing) to sample surface induced by Ga + ion beam implantation during Pt protection film deposition was proved by TEM observation, and the method to avoid this damage are proposed.

Effect of BOE etching time on wire bonding quality

The dependence of wire bond-pull strength on the morphology of the underlying polycrystalline silicon (poly-Si) beneath the bondpad metal is studied using atomic force microscopy (AFM). Statistical analysis shows that the roughness of the poly-Si is correlated with the wire bond-pull strength. The correlation is believed to be due to the effectiveness of thermal dissipation through poly-Si during the wire bonding process. Statistical analysis also shows that the roughness of the poly-Si is correlated to the buffered oxide etch (BOE) etching time before the bondpad metal deposition. In this work, it is concluded that the BOE etching time has a significant effect on the wire bonding quality. The roughness parameter that links the BOE etching time to the wire bond-pull strength is found to be the localization factor.

Failure mechanism study for high resistance contact in CMOS devices

In advanced CMOS manufacturing, when aspects including contacts with W plugs are being miniaturised, high resistance contacts causing low yield becomes a common issue. In failure analysis, contact failures such due to insufficient trench etching and particle blocking which can cause extremely high resistance or opens are relatively easy to isolate and identify. However, for those contacts with resistance marginally higher than normal, the root cause is very difficult to identify by traditional methods like passive voltage contrast (PVC) and scanning electron microscopy (SEM), or focused ion beam (FIB) technology, which is quite successful for the open contact cases. This contact resistance variation is normally due to the narrow process window or process parameters drifting and may lead to relatively low yield. Direct observation of these contacts by transmission electron microscopy (TEM) provides detailed microstructural and chemical information which correlates to the failure and are unobtainable by other material analysis techniques. In this paper, we report a novel failure mechanism of the high resistance contact revealed by TEM study. Direct evidence is provided to show the impact of process changes on the contact structure which may correlate to the high resistance.

Failure analysis of 65nm technology node SRAM soft failure

In this paper, a real case of 65 nm technology node SRAM failure was studied. The failure of the SRAM is soft failure, so the traditional method was failed to localize the exact position of the failed transistor. To find the root cause, the biased current image-Atom Force Microscopy combined with Atom Force Probing was used to probe the failed cell of the SRAM to find one abnormal pass-gate transistor. Theoretical analysis combined with the probing result was performed to find the failure location. Then current image was used to confirm the failure location. According to the AFP result, TEM and EDX were performed along the active of the pass-gate. Incomplete silicidation was observed under the active contact which correlated well to the electrical analysis result.

High resistance via induced by marginal barrier metal step coverage and F diffusion

In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (Hamanaka et al., 1994; Chen et al., 1995). Compared to the open via contact, a high resistance via due to insufficient process margin is more difficult to isolate and physically characterize. It has been reported that F contamination induces resistance variations and leads to timing issues in the SRAM (Perungulam et al., 2000). However, understanding of the F diffusion mechanism through the Ti-TiN barrier metal layer and the correlation with the barrier metal properties and thus the failure mechanism during reliability testing is still limited. In this paper, the failure mechanism of high via resistance caused by F diffusion was studied by transmission electron microscopy (TEM) at different process split steps. Properties of different barrier metal layers by different processes are also discussed.

Application of FIB circuit edit combined with TIVA in advanced failure analysis

This paper presented a failure analysis methodology to overcome the difficulties of fault location encountered by pin leakage and some testing parameter failures in a mixed signal device. These types of failure generally cannot be solved by traditional electrical failure analysis methods.

Study on SRAM soft failure using planar-view transmission electron microscopy techniques

Soft failure in static random access memory (SRAM), where there are several mechanisms related to it, is a kind of major obstruction to improve the yield. Transmission electron microscopy (TEM) is a powerful failure analysis tool, which has a high spatial resolution and is widely used in IC failure analysis with the shrinkage of integrated circuit to a nano-level transistor. Planar-view TEM techniques have great advantages in finding failure location and mechanism. In this paper, two kinds of soft failure root causes are identified by the planar-view TEM techniques.

Challenges in barrier and seed layers characterization of copper technology IC devices

Ta barrier and Cu seed layer characterization becomes extremely challenging with devices scaling down into 0.13 /spl mu/m and 90 nm regime. This paper aims at providing a feasible solution for this challenge from both sample preparation and TEM imaging perspectives. Different sample preparation and imaging techniques are compared here.