E. Gauja

Controlled shallow single-ion implantation in silicon using an active substrate for sub-20-keV ions

We demonstrate a method for the controlled implantation of single ions into a silicon substrate with energy of sub-20‐keV. The method is based on the collection of electron-hole pairs generated in the substrate by the impact of a single ion. We have used the method to implant single 14‐keV P31 ions through nanoscale masks into silicon as a route to the fabrication of devices based on single donors in silicon.

Demonstration of a silicon-based quantum cellular automata cell

We report on the demonstration of a silicon-based quantum cellular automata (QCA) unit cell incorporating two pairs of metallically doped (n+) phosphorus-implanted nanoscale dots, separated from source and drain reservoirs by nominally undoped tunnel barriers. Metallic cell control gates, together with Al–AlOx single electron transistors for noninvasive cell-state readout, are located on the device surface and capacitively coupled to the buried QCA cell. Operation at subkelvin temperatures was demonstrated by switching of a single electron between output dots, induced by a driven single electron transfer in the input dots. The stability limits of the QCA cell operation were also determined.

Progress in silicon-based quantum computing

We review progress at the Australian Centre for Quantum Computer Technology towards the fabrication and demonstration of spin qubits and charge qubits based on phosphorus donor atoms embedded in intrinsic silicon. Fabrication is being pursued via two complementary pathways: a ‘top–down’ approach for near–term production of few–qubit demonstration devices and a ‘bottom–up’ approach for large–scale qubit arrays with sub–nanometre precision. The ‘top–down’ approach employs a low–energy (keV) ion beam to implant the phosphorus atoms. Single–atom control during implantation is achieved by monitoring on–chip detector electrodes, integrated within the device structure. In contrast, the ‘bottom–up’ approach uses scanning tunnelling microscope lithography and epitaxial silicon overgrowth to construct devices at an atomic scale. In both cases, surface electrodes control the qubit using voltage pulses, and dual single–electron transistors operating near the quantum limit provide fast read–out with spurious–signal rejection.

Ion-beam-induced-charge characterisation of particle detectors

Abstract Ion-beam-induced-charge collection (IBIC) in a nuclear microprobe has been used to characterise detectors for the measurement of particles over a median energy range (100 keV–1 MeV). Three standard detector devices have been studied: a PIPS detector with a buried (ion-implanted) junction structure, a Schottky barrier junction device and a PN-junction photodiode. A 2.0 MeV focussed helium ion beam was used to probe the active area of each device with a spatial resolution ∼1–2 μm, to quantify the thickness of the dead layer, the charge collection response and the reduction in charge collection efficiency induced by ion-beam damage.

The use of etched registration markers to make four-terminal electrical contacts to STM-patterned nanostructures.

We demonstrate the use of etched registration markers for the alignment of four-terminal ex situ macroscopic contacts created by conventional optical lithography to buried nanoscale Si:P devices, patterned by hydrogen-based scanning tunnelling microscope (STM) lithography. Using SiO(2) as a mask we are able to protect the silicon surface from contamination during marker fabrication and can achieve atomically flat surfaces with atomic-resolution imaging. The registration markers are shown to withstand substrate heating to approximately 1200 degrees C and epitaxial overgrowth of approximately 25 nm Si. Using a scanning electron microscope to position the STM tip with respect to the markers, we can achieve alignment accuracies of approximately 100 nm, which allows us to contact buried Si:P structures. We have applied this technique to fabricate P-doped wires of different widths and measured their I-V characteristics at 4 K, finding ohmic behaviour down to a width of approximately 27 nm.

Technology computer-aided design modelling of single-atom doping for fabrication of buried nanostructures

Future quantum devices may exploit arrays of dopants positioned with nanoscale precision in an intrinsic semiconductor matrix. One proposal for the fabrication of such an array is by the implantation of single low-energy dopant ions into prefabricated cells within the device, the arrival of each dopant being detected electrically. With the aid of technology computer-aided design (TCAD) modelling, we outline an electrical registration process which makes use of appropriately biased electrodes incorporated within the device to detect the space charge induced within the near-intrinsic substrate by a single-ion implant. A series of simulations aimed at optimizing the charge detection efficiency in such detectors are described, and found to be in good agreement with experimental measurements conducted to characterize fabricated test structures via high-energy He-ion implantation. We demonstrate this fabrication strategy to offer the potential of creating scalable arrangements of dopants for extended nanoscale device applications. Our interest in this scheme is the development of the Kane solid-state quantum computer (Kane B E 1998 Nature 393 133), which exploits as qubits31P atoms embedded with nanoscale precision in an array, within a pure28Si MOS architecture.

IBIC characterisation of novel detectors for single atom doping of quantum computer devices

Abstract Single ion implantation and online detection is highly desirable for the emerging application, in which single 31P ions need to be inserted in prefabricated silicon cells to construct solid-state quantum bits (qubits). In order to fabricate qubit arrays, we have developed novel detectors that employ detector electrodes adjacent to the prefabricated cells that can detect single keV ion strikes appropriate for the fabrication of shallow phosphorus arrays. The method utilises a high purity silicon substrate with very high resistivity, a thin SiO2 surface layer, nanometer masks for the lateral positioning single phosphorus implantation, biased electrodes applied to the surface of the silicon and sensitive electronics that can detect the charge transient from single keV ion strikes. A TCAD (Technology Computer Aided Design) software package was applied in the optimisation of the device design and simulation of the detector performance. Here we show the characterisation of these detectors using ion beam induced charge (IBIC) with a focused 2 MeV He ions in a nuclear microprobe. The IBIC imaging method in a nuclear microprobe allowed us to measure the dead-layer thickness of the detector structure (required to be very thin for successful detection of keV ions), and the spatial distribution of the charge collection efficiency around the entire region of the detector. We show that our detectors have near 100% charge collection efficiency for MeV ions, extremely thin dead-layer thickness (about 7 nm) and a wide active region extending laterally from the electrodes (10–20 μm) where qubit arrays can be constructed. We demonstrate that the device can be successfully applied in the detection of keV ionisation energy from single events of keV X-rays and keV 31P ions.

Characterization and optimisation of PECVD Silicon Nitride as dielectric layer for RF MEMS using reflectance measurements

Synthesis of Silicon Nitride thin films is important in the semiconductor industry. The properties of the films make them valuable for oxidation masks, protection and passivation barrier layers, etch stop layer and inter level insulators. In the present study, we prepared silicon nitride films with different refractive index. We used various conditions of PECVD atmosphere with the purpose of obtaining high quality near stoichiometric films. Different deposition routines were employed, including variable flow ratio of silane and ammonia on to a silicon substrate. The quality and stoichiometry of the film was investigated using reflectance measurements of the films. Measured process parameters were the deposition rate, film thickness, refractive index, breakdown voltage, dielectric constant, surface morphology and film composition. The thickness of the film was measured by using AFM, DEKTAK and ellipsometer measurements. Fitting of reflectance spectra with WVASE ellipsometric software provided us with optical constants for silicon nitride and allowed analysis of the films. A Bruggeman effective medium approximation was utilized to model the refractive index of the films. Reflective measurements were carried out in the range 210 nm-2500 nm.

Nanofabrication processes for single-ion implantation of silicon quantum computer devices

We describe progress in nanofabrication processes for the production of silicon-based quantum computer devices. The processes are based on single-ion implantation to place phosphorus-31 atoms in accurate locations, precisely self-aligned to metal control gates. These fabrication schemes involve multi-layer resist and metal structures, electron beam lithography and multi-angled aluminium shadow evaporation. The key feature of all fabrication schemes is an integrated combination of patterns in different resist and metal layers that together define self-aligning metal gate structures as well as channels down to the substrate through which to implant the phosphorus. Central to this process is a new technique that allows for control and detection of the implantation process at a single-ion level.

Deep level transient spectroscopy study for the development of ion-implanted silicon field-effect transistors for spin-dependent transport

A deep level transient spectroscopy (DLTS) study of defects created by low-fluence, low-energy ion implantation for development of ion-implanted silicon field-effect transistors for spin-dependent transport experiments is presented. Standard annealing strategies are considered to activate the implanted dopants and repair the implantation damage in test metal-oxide-semiconductor (MOS) capacitors. Fixed oxide charge, interface trapped charge and the role of minority carriers in DLTS are investigated. A furnace anneal at 950 °C was found to activate the dopants but did not repair the implantation damage as efficiently as a 1000 °C rapid thermal anneal. No evidence of bulk traps was observed after either of these anneals. The ion-implanted spin-dependent transport device is shown to have expected characteristics using the processing strategy determined in this study.