Keiichiro Kashihara

Suppression of Anomalous Gate Edge Leakage Current by Control of Ni Silicidation Region using Si Ion Implantation Technique

It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby current and yield for 65nm-node SRAM are greatly improved. This novel technique has high potential for 45nm and 32nm CMOS technology

Improvement of thermal stability of nickel silicide using N 2 ion implantation prior to nickel film deposition

Nitrogen ion implantation (N2 I.I.) prior to Ni film deposition successfully suppresses the agglomeration of nickel silicide (NiSi) formed on arsenic doped silicon substrate in NMOS region, and drastically improves the thermal stability of its resistivity at narrow lines. Using this technique, lower sheet resistance of NiSi narrow line can be kept at high annealing temperature of 650degC for 30 sec. Comparing with argon ion implantation (Ar I.I.), only the N2 I.I. can suppress the agglomeration of NiSi. These results suggest that the implanted N2 ions form Ni-N or Si-N bonds in NiSi, and as a result, these bonds suppress the excess diffusion of Ni and Si atoms during thermal process

Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique

A novel low-leakage-current nickel self-aligned-silicide (SALICIDE) process in n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on Si(110) substrates is reported. Anomalous nickel silicide encroachment in the direction in nMOSFETs on Si(110) substrates is found for the first time. This encroachment causes anomalous off-state leakage current (Ioff) in nMOSFETs on Si(110) substrates. In particular, in the case of the channel on Si(110) substrates, Ni atoms easily diffuse in the direction, and nickel silicide preferentially grows in the direction. As a result, anomalous leakage current between the drain and the source occurs, and the leakage current seriously degrades transistor performance. In order to overcome these problems, we propose a method of suppressing anomalous Ioff on Si(110) substrates by Si+ ion-implantation technique prior to the nickel SALICIDE process. This method is effective for suppressing the encroachment of nickel silicide and realizing low-leakage complementary metal–oxide–semiconductor (CMOS) devices on Si(110) substrates.

Anomalous Gate-Edge Leakage Current in nMOSFETs Caused by Encroached Growth of Nickel Silicide and Its Suppression by Confinement of Silicidation Region Using Advanced

The anomalous gate-edge leakage current in n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs), which is caused by the encroached growth of nickel silicide across the p-n junction, is first reported. Furthermore, this encroached growth, which is caused by the isotropic and rapid diffusion of Ni atoms during the silicidation annealing, is successfully suppressed by the advanced Si+ ion-implantation (Si-I.I.) technique. Using the Si-I.I. technique, both the anisotropic silicidation to the perpendicular direction and the phase transition from Ni2Si to NiSi are enhanced by the introduction of damaged layers into Si substrates, such as vacancy and amorphous Si layers, and as a result, the silicidation region is confined at the source and drain regions. In addition, we propose a new evaluation method for the quantitative analysis of the encroached growth based on its growth properties, namely, the variability of encroached growths, which is three standard deviations of the roughness at silicide edges. The usefulness of this simple analysis for a large number of nMOSFETs is also demonstrated.

\hbox{Si}^{+}

A novel low leakage-current Ni SALICIDE process in nMOSFETs on Si(110) is proposed. It is found for the first time that the anomalous off-state leakage-current (Ioff) in nMOSFETs on Si(110) is caused due to the inherent Ni silicide encroachment toward the channel region. Especially, <110> channel on Si(110) has fatal defect for CMOS fabrication. We propose two methods to suppress the anomalous Ioff, the creative ingenuity of design layout within SRAM and Si ion implantation (Si I.I.) technique. These two methods are quite effective to realize high performance and low cost CMOS devices on Si(110).

Ion-Implantation Technique

A novel process technology to realize a thick Pt bottom electrode is developed, particularly for facilitating the use of sputter-BST capacitors. The sputter-BST capacitor fabricated with this technology gives a production-worthy yield and maintains initial electrical properties after finishing the back-end process, including the Al wiring and the plasma SiN-passivation. By using this technology, it is feasible to obtain a reliable BST capacitor in the 0.16 /spl mu/m-geometry, with the achievement of BSTs Teq, SiO/sub 2/-equivalent thickness, of 0.40 nm and a 300 nm-high bottom electrode.

A Novel Low Leakage-Current Ni SALICIDE Process in nMOSFETs on Si(110) Substrate

A novel capacitor technology has been developed for 0.15 µm embedded dynamic random access memory (DRAM). Platinum as electrodes and barium strontium titanate (BST) as dielectrics are used in the capacitor. The BST dielectrics is a stack of two layers. The nucleating bottom layer is deposited by sputtering and the top bulk layer is deposited by chemical vapor deposition (CVD). The two-step deposition process is established with high reliability without N2 high-temperature annealing. Moreover, both thermal stability and reductive stability of the BST capacitors are improved by introducing modulated oxygen-doping into the Pt top electrodes. The degradation mechanism of the BST capacitors by annealing in the back end process was revealed. Oxygen atoms doped into the top electrode diffuse to the interface between the bottom electrode and the metal nitride barrier layer, and oxidize the metal nitride. The modified BST capacitors maintained low leakage current and sufficient capacitance after 500°C N2 annealing and 400°C H2 annealing. These BST capacitors have been integrated into the 0.15 µm rule-embedded DRAM having a capacitor under bit-line (CUB) structure and four-level metallizations.

A manufacturable integration technology of sputter-BST capacitor with a newly proposed thick Pt electrode

This is the first paper to reveal the formation mechanism of the abnormal growth of nickel silicide that causes leakage-current failure in complementary metal-oxide- semiconductor (CMOS) devices by using advanced transmission electron microscope (TEM) techniques: electron tomography and spatially-resolved electron energy-loss spectroscopy (EELS). We reveal that the abnormal growth of Ni silicide results in a single crystal of NiSi2 and that it grows toward Si <;110> directions along (111) planes with the Ni diffusion through the silicon interstitial sites. In addition, we confirm that the abnormal growth is related to crystal microstructure and crystal defects. These detailed analyses are essential to understand the formation mechanism of abnormal growths of Ni silicide.

Pt/BaxSr(1-x)TiO3/Pt Capacitor Technology for 0.15 µm Embedded Dynamic Random Access Memory

We have performed a detailed analysis of crystal defects in high-performance p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with embedded SiGe source/drain (S/D), using low-angle annular dark field (ADF) scanning transmission electron microscopy (STEM) and electron tomography. We achieved successful results in three-dimensional visualization of crystal defects for the first time. Consequently, we have discussed about the three-dimensional physical geometric relationship between crystal defects and device architecture. This approach is sure to contribute to the development of advanced complementary metal–oxide–semiconductor (CMOS) devices using strained silicon technology.

Analysis of Junction Leakage Current Failure of Nickel Silicide Abnormal Growth Using Advanced Transmission Electron Microscopy

We performed detailed analysis of Ni silicide discontinuities induced by agglomeration that causes the increasing electric resistance in high-performance CMOS devices by using advanced physical analysis techniques. We confirmed that the agglomeration of the Ni silicide is related to elongated-triangular- shaped-splits — which we call delta-shaped-splits — which cause discontinuities that occur at small-angle grain boundaries pinned by boron clusters even with small stress. We successfully determined the formation mechanism of the Ni silicide discontinuities in detail. It is essential to develop a highly reliable Ni salicide process, especially for 45 nm node high performance devices and beyond.