E. R. Hsieh

The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors

The source/drain in an n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with solid phase epitaxial (SPE) implanted Si:C before the spacer formation is proposed. Compared to the conventional nMOSFET with SPE implanted Si:C after the spacer formation, it brings in proximity to the device channel and shows great improvement of electron mobility via the stronger tensile strain effect. Experimental measurements showed that the electron mobility in the proposed process is increased by 105% over that of the control devices. At a gate length of 40 nm, an increase of more than 67% for the drain current, comparing to those of the conventional Si:C source/drain nMOSFET, has been achieved.

The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found

The impact of multi-level RTN on SRAM cells bas been experimentally demonstrated on both planar and trigate CMOS devices. First, to study multi-level RTN, a simple experimental method has been developed to take the 2D profiling of multi-traps in both oxide depth (vertical) and channel(lateral) directions in the gate oxide. Then, the role of traps in the switching mechanisms of SRAM cells has also been examined. Results show that the multi-traps will degrade RSNM (read static noise margin), as well as cause transition failure in SRAM operations. This is the first being observed and reported that will be considered as a major criterion in the future low voltage design of SRAM cells.

The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique

Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or NBTI-stress, induce the Vth variations. To identify these traps, for the first time, a unique random trap profiling feasible for 3D device applications has been demonstrated on trigate devices. For such devices, the oxide traps are generated not only near the drain side but also on the sidewall, after hot carrier (HC) and NBTI stresses. More importantly, the Vth variation in pMOSFET under NBTI becomes much worse as a result of an additional surface roughness effect. This method provides us a valuable tool for the diagnosis of reliability in 3D devices (e.g., FinFET).

More strain and less stress- the guideline for developing high-end strained CMOS technologies with acceptable reliability

In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65 nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (Nit) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.

The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices

For the first time, the breakdown path induced by BTI stress can be traced from the RTN measurement. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths are revealed. The soft-breakdown path is in a shape like spindle, while the hard breakdown is like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices.

The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors

An effect, called random trap fluctuation (RTF), is proposed to study the threshold voltage (Vth) fluctuation of metal oxide semiconductor field effect transistors (MOSFETs) under Fowler-Nordeim (FN) or hot carrier (HC) stress condition. Experiments have been demonstrated on n-channel MOSFETs, and it was found that not only the random dopant fluctuation (RDF) but also the stress-induced traps vary the Vth fluctuation. More importantly, the stress-induced trap barrier determines the Vth fluctuation. For devices after FN stress, Vth fluctuation is enhanced since the trap barrier regulates the transporting carriers. For devices after HC stress, Vth fluctuation is supressed since the carriers are backscattered into the channel by the trap barrier and fewer carriers with higher energy pass through the barrier. These results provide us a clear understanding on another source of Vth fluctuations in addition to the RDF as devices are further scaled.

The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown

For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<; 50μA), fast speed (~20μsec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.

The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement

The evolution of gate-current leakage path has been observed and depicted by RTN signals on metal-oxide-silicon field effect transistor with high-k gate dielectric. An experimental method based on gate-current random telegraph noise (Ig-RTN) technique was developed to observe the formation of gate-leakage path for the device under certain electrical stress, such as Bias Temperature Instability. The results show that the evolution of gate-current path consists of three stages. In the beginning, only direct-tunnelling gate current and discrete traps inducing Ig-RTN are observed; in the middle stage, interaction between traps and the percolation paths presents a multi-level gate-current variation, and finally two different patterns of the hard or soft breakdown path can be identified. These observations provide us a better understanding of the gate-leakage and its impact on the device reliability.

The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO 2 high-k metal gate 28nm CMOS devices

A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the Vth degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.

Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM

A new gate current variation (σIg) has been proposed for the first time and demonstrated on the trigate devices. It was found that gate current variation can serve as an indicator of the gate sidewall surface roughness. A new theory has then been developed and verified experimentally on trigate devices with various fin heights. Results show that surface roughness increases with the increasing fin height. In addition, hot carrier and NBT stresses have also been performed for trigate CMOS devices. It was found that NBTI exhibits the worst Ig variation. Finally, this theory has been tested on the SRAM to examine the standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.