R. M. Huang

The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found

The impact of multi-level RTN on SRAM cells bas been experimentally demonstrated on both planar and trigate CMOS devices. First, to study multi-level RTN, a simple experimental method has been developed to take the 2D profiling of multi-traps in both oxide depth (vertical) and channel(lateral) directions in the gate oxide. Then, the role of traps in the switching mechanisms of SRAM cells has also been examined. Results show that the multi-traps will degrade RSNM (read static noise margin), as well as cause transition failure in SRAM operations. This is the first being observed and reported that will be considered as a major criterion in the future low voltage design of SRAM cells.

The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique

Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or NBTI-stress, induce the Vth variations. To identify these traps, for the first time, a unique random trap profiling feasible for 3D device applications has been demonstrated on trigate devices. For such devices, the oxide traps are generated not only near the drain side but also on the sidewall, after hot carrier (HC) and NBTI stresses. More importantly, the Vth variation in pMOSFET under NBTI becomes much worse as a result of an additional surface roughness effect. This method provides us a valuable tool for the diagnosis of reliability in 3D devices (e.g., FinFET).

Segmented tri-gate bulk CMOS technology for device variability improvement

Tri-gate bulk MOSFETs are realized using a simple shallow-trench-isolation (STI) oxide recess approach. The tri-gate structure together with a retrograde body doping profile provides for superior electrostatic integrity, particularly for narrow fin widths, to reduce variability in transistor performance. The benefits of tri-gate bulk MOSFET technology for 28nm-node 6-T SRAM cells (0.149um2 bit-cell area) are assessed. As compared against planar cells, tri-gate cells show less degradation in static noise margin (SNM) and write margin (WRM) variations with decreased operating voltage. Thus, the STI-recess process provides a simple means for reducing device performance variability to facilitate CMOS technology scaling.

Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM

A new gate current variation (σIg) has been proposed for the first time and demonstrated on the trigate devices. It was found that gate current variation can serve as an indicator of the gate sidewall surface roughness. A new theory has then been developed and verified experimentally on trigate devices with various fin heights. Results show that surface roughness increases with the increasing fin height. In addition, hot carrier and NBT stresses have also been performed for trigate CMOS devices. It was found that NBTI exhibits the worst Ig variation. Finally, this theory has been tested on the SRAM to examine the standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.

New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress

A new effect, called random trap fluctuation(RTF), is proposed to study the impact of hot carrier stress on the device variability. It was found that not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or FN-stress, induce the Vth variation. After the FN stress, it was found that Vth variation is worse in pMOSFETs due to stress-induced interface traps. While, under the HC stress, different Vth variations were found for nMOSFETs and pMOSFETs. The Vth variation is enhanced in pMOSFETs due to RTF and reduced in nMOSFET as a result of the Trap Blocking Effect (TBE). RTF in pMOSFET might be the dominant factor of CMOS reliability for future generations.

The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices

The variation of saturation drain current (I_d,sat), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of I_d,sat is originated from V_th,sat and saturation velocity (V_sat), while the variation of V_th,sat comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that V_sat dominates the variation of I_d,sat. From the transport theory, V_sat is further decomposed into V_inj and B_sat, showing that V_inj is the dominant factor of I_d,sat variation. The faster the V_inj is, the less the I_d,sat variation becomes. If one improves the injection velocity, then the variation of I_d,sat can be suppressed. This has been one of the significant benefits of strained silicon technology in CMOS device scaling.

Geometric variation: A novel approach to examine the surface roughness and the line roughness effects in trigate FinFETs

A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.

A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, Avt, Agm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.

The understanding of the bulk trigate MOSFET's reliability through the manipulation of RTN traps

The manipulation of RTN-trap profiling bas been experimentally demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. This is the first being reported that the positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones.

New criteria for the RDF induced drain current variation considering strain and transport effects in strain-silicon CMOS devices

In this paper, we have studied the Id variation in linear and saturation region by considering the strain-induced effect and the carrier transport of strained CMOS devices. It was found that the origin of linear Id variation comes from the mobility scattering; while in saturation region, the Id variation is dominated by the injection velocity. The higher the injection velocity is, the smaller the saturation Id variation becomes. These results provide us a guideline for achieving good variability control of strain-based CMOS technologies.