Steve S. Chung

AHE: A New Low Voltage/High Speed Programming Scheme for Both N- and P-Channel Flash EEPROM's

Two strategies are commonly used to design high performance ETOX flash cells. One is based on the cell structure approach such as p-channel[l] or p-floating gatef2l, and the other one is using different operation schemes. In the design of low voltage or low power flash cells, several programming schemes have been of interests, such as CHISEL[3], DAHE(Drain Avalanche Hot Electron) [4], and SCIHEIS] etc, For the first time, we report a new programming scheme which is well suited for both nand p-channel flash cells. This programming is achieved by substrate bias enhanced Avalanche Hot-Electron (AHE) injection. In particular, it allows progranrming at very low terminal voltages within +5V and -5V. ln ter.ms of the performance, the present scheme is faster than CHE or BBHE [6] scheme. In terms of the reliabilities, better gateand drain-disturb, reasonable endurance, can be achieved for both nand p-channel cells owing to a low voltage operation. Also, for the retention characteristics, AHE scheme shows much better benefit for n-channel cells. Device Preparation and Measurements The cell structure used in this study is a conventional stacked-gate(ETOx) flash memory cell fabricated by 0.35pm triple well technology both for the n-channel and p-channel cells. The thickness of tunnel oxide/effective ONO interpoly dielectric are 100fu210A and 90.4/165A for n-channel and p-channel cells respectively. Fig. 1 shows the schematic diagram of the new AHE scheme along with the operating conditions. Note that the terminal voltages are kept within +5V and -5V for programming in the new scheme. Results and Discussion A. The Scheme and Cell Perfonnance The mechanism of the new scheme is as follows. First, the drain/substrate junction is biased in the avalanche region, from which electrons and holes are generated. Then, the hot electrons will surmount the barrier and contribute to the gate current via an appropriate field between the gate and the substrate or the drain. Fig. 2 shows the gate and drain current of n-cells. The injection effrciency defined as I6/Ip is about tO-5-tO-6 for both type of cells using AHE scheme. It is larger than that of the conventional CHE and less than that of the BBHE[6]. The programming characteristics of AHE for nand p-channel cells are shown in Figs. 3 and 4, respectively. AHE scheme is always faster than CHE scheme in n-cell and BBHE in p-cell. In extreme case, the prograilrming speed as fast as nano-second range can be achieved. The convergence speed ofn-channel cell using AHE scheme is faster than that of normal CHE scheme. B. CeIl Reliabilities Disturb Characteristics: For the evaluation of disturb, the gate and drain disturb will be taken into consideration. Fig. 5 shows the results of gate distwb for the new AHE scheme and their comparison with conventional scheme in both nand p-channel cells respectively. The gate disturb is nearly eliminated in the present scheme since much lower control gate voltage is used in Extended Abstracts of the 2002 lnternational Conference on Solid State Devices and Materials, Nagoya, 2002, pp. 612-613 AHE: A New Low Voltage ftlighspeed Programming Scheme for Both Nand P-Channel Flash EEPROMs Steve S. Chung, Y. J. Chen, T. C. Chuang, H. H. Chen*, and Gary Hong* Department of Electronic Engineering, National Chiao Tung University, Taiwan *UMC, Science-based Industrial Park, Hsinchu, Taiwan the new scheme. This is one of the major benefit. Through the help of a substrate bias, drain disturb can also be greatly reduced for p-channel cells as given in Fig. 6, in which a 3-order improvement of the drain disturb can be achieved. However, the drain disturb is almost the same by using either the present scheme or CHE scheme, Data Retention Characteristics: The experimental data retention characteristics are shown in Fig. 7. This figure shows the threshold voltage shift of the cells before and after P/E cycles baked at 250oC. It is obvious that AHE has a much better data retention by comparing with that of CHE. However, no advantage for the p-cell based on the AHE scheme. But, this can be remedied by a device drain engineering. Endurance: The reliability of the flash cell with AHE both for nand p-channel cells has also been examined for the endurance characteristics. The CHE for n-channel cells and BBHE for pchannel cells are used as a reference. All of the experimental cells use channel Fowler-Nordheim(FN) for erase. Fig. 8 shows the endurance characteristics for n-channel cells. After the cycling, similar results of the window closure are observed for ncell. However, for the p-cells, the window closure is relaxed for both AHE and BBHE schemes. (P-channel cell endurance will be shown during the presentation). Comparison with Reported Schemes: The present scheme shows slight difference with reported schemes but exhibits uunique features. For a comparison, please see the GIDL measurement in Fig. 9. The present AHE scheme is faster and reliable than the CHISELI3] scheme since more electron sources are generated in the drain which gives large gate current injection. SCIHE[5] is a combination of CHISEL and DAHE[4], which grves a poorer reliability by comparing with the present AHE scheme. Although the DAHE scheme has better reliability, it has disadvantages with a high voltage and lower speed. In short, a low voltage operation should be achieved by a substrate bias and with suitable sources of electrons for injection purpose. In summary, w€ demonstrated a new prograrnming scheme, substrate-bias enhanced AHE, for both nand p-channel flash cells. It is achieved by a combination of the avalanche hot electron injection in the drain and an applied substrate bias. This scheme features low voltage and high speed operation. Results show that the present scheme exhibits many advantages for applications to nor p-channel cell. These include a faster progrilnming speed, low voltage,low power, faster convergence, better gate disturb, ffid drain disturb characteristics. Moreover, in extreme case, a record high speed with 20 nsec programming for a state-of-the-art ETOX flash cell technology can be achieved. Also, it is well suited for low voltage and high reliability applications. Acknowledgments This work was sponsored by the NSC, Taiwan, under contract No. NSC892218-E009-110. References tll C. C. -H. Hsu et al., Extended Abs. of SSDM,p. 140,1992. t2) S. S. Chung et al., in Symp.on WSI Technologt, p. 19, 1999. t3l J. Bude et a1., in IEDM Tech. Dig.,p.279,1997. t4l S. Haddad et al., in Symp. on VLil Technologt,p.52,1996. t5l C. -Y. Hu et al., inIEDM Tech. Dig.,p.283,1995. t6l T. Ohnakado et al., inIEDM Tech. Dig.,p.279,1995.

New Mechanisms and the Characterization of Plasma Charging Enhanced Hot Carrier Effect in Deep-Submicron N-MOSFET's

Plasma etching will induce two types of damage plasma charging damage and plasma edge damage. Both will cause the degradation of various electrical characteristics. In this paper, we present a new observation of a plasma charging enhanced damage ffict and, its conelation with device reliability. Based on the Charge Pumping (CP) profiling technique, plasma charging enhanced edge damage indeed exists and will enhance device degradation after hot carrier (HC) stress. This phenomenon has been verified for devices with four types of antenna structures. Results show that the localized N;, in the drain region will be further enhanced not only by the plasma charging but also by the HC stress. This technique can be used as a good monitor of the antenna effect studies. l.Introduction Plasma etching process has become one of the key technologies in modern IC manufacturing. Howeve_1, it will induce two different types of damage [1-2]. One is the plasma charging damage (in the gate oxide and channel region), and the other one is the plasma edge damage (at the corner of poly-Si gate region). The former is due to plasma-induced Jpp cunent flowing through the gate oxide, while the latter results from the direct plasma interaction with the Si-wafer and the oxide near the poly-Si gate edges. In previous studies, none has been reported on the interaction of these two plasma damage in short channel devices. Therefore, we will present new findings on how both damage together will affect the device reliability, in particular for short channel legth devices. In this study, based on the experimental results, we will first propose a new mechanism to describe the plasma charging enhanced edge damage. CP profiling technique [3-4] will be used to extract this plasma damage effect. For the first time, this approach can provide a direct evidence of this enhanced damage. Finally, three plasma damage-curing processes will also be verified by the present approach. 2. Device Fabrication and Measurements The devices used in this work were fabricated using 0.35pm nMOSFETs technology. Four kinds of antenna structures were used as shown in Fig. 1. These n-MOSFETs have 38A gate oxide thickness and shallow S/D n+ extension. The n+ S/D extensions are formed using implanted Arsenic with dose and energy of 4.0xl0lacm-2 and l0KeV respectively. For the HC reliability test of rhese devices, Ig.ru* stress was used. 3. Results and Discussion A. A 4-phase Plasma Daniage Mechanism There are 4 phases involved in the generation of the plasma damage, as illustrated in Fig. 2. From the beginning, plasma charging degrades oxide quality by FN current (Fig. 2(l)). Then, plasma edge damage is generated by direct ion bombardment (Fig. 2(2)). This edge damage was repaired after the poly-reoxidation process for the tested devices. During the follow-up plasma etching of the antenna structure (e.g., capacitance, interconnected line), an enhanced edge damage occurs at the poly-Si gat edge, since most of the current path goes though the edge due to a weaker oxide barrier (Fig. 2(3)). After being fabricated, devices are then tested with HC stress, which will induce damage near the drain region (Fig. 2(a)). Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, Sendai, 2000, pp. 16-17 the Characterization of Plasma Charging Enhanced Hot Carrier Effect in Deep-Submicron N-MOSFETs S. J. Chen, H. L. Kao, Steve S. Chung, C. C. Chen, C. Y. Chang, and H. C. Lin* Department of Electronic Engineering, National Chiao Tung University, Taiwan. * National Nano Device Lab., Hsinchu, Taiwan. B. Enhanced Edge Damage for Deaice Scaling Fig. 3 shows the technique used to correlate CP current, Ni1 and Ip degradation. Fig. 3(a) is the measured CP currents for 4 different test devices. Fig. 3(b) shows the maximum CP currents (at Vrl= 2V of 3(a)) as a function of channel length. Also, the interface states and Ip degradation are shown in Fig. 3(c) and (d) respectively. It was found that: ( 1 ) The amount of device degradation is device (4)>(3)>(2)>( I ) due to electron shading effect t5-61. (2) For short channel devices, Ip degradation will be further enhanced. (3) The generated interface state is proportional to the Ip degradation in Fig. 3(d). Therefore, we propose a different mechanism (in Fig. 4) to describe the above observations. For long channel device, plasma charging damage is dominant, while for short channel devices, a so called plasma charging enhanced effect is observed at the edge. This enhanced effect is caused by the plasma process during step (3) as suggested in Fig. 2. Conventional studies said that plasma charging will dominate device degradation for long channel devices, while plasma induced edge damage will dominate device degradation when devices are scaled down (Figs. 3(c) and (d)). However, we found that HC effect (in Figs. 3(c) and (d)) is independent of plasma charging damage when channel length is long enough, while the HC effect is enhanced by plasma charging damage for short channel devices. C. Vefification of Plasma Charging Enhanced Edge Damage In order to justify the above reasoning, CP profiling technique[3] has been employed to calculate the interface states (N;,). Major findings are given in Fig. 5. Figs. 5(a) and 5(b) show the CP currenrs for fresh devices and the calculated Ni due to plasma charging enhanced edge damage. Figs. 5(c) and 5(d) show the CP currenrs before and after HC stress and the associated Nl due to plasma charging enhanced HC effect. Fig. 6 shows the position of the maximum electrical field. One major resulr from Fig. 5(d) is that the maximum of plasma charging enhanced damage is even larger than that of HC induced da.mage. Energy band diagram in Fig.7 can be used to explain that the position of this plasma enhanced edge damage is located at B-B* in Fig. 6, which is vulnerable to the charging current path. To suppress the edge damage, three different processes have been demonstrated in Fig. 8 by using nitrided gate oxide, N2O ambience for poly reoxidation, and the control of overetch time during plasma processing. Results show that the generation of interface states and hence the device Ip degradation can be effectively reduced by the above three different techniques. In summary, a new 4-phase plasma induced damage mechanism (Fig. 2) has been proposed for antenna effect studies. It was found that with the scaling of device channel length, the plasma charging enhanced edge damnge (Fig.5(d)) will dominate the device degradation. In other words, plasma charging through the antenna structure will enhance the damage at poly-Si gare edge which makes the gate oxide be more fragile in this region. As a consequence, devices will exhibit a much larger interface state at the near drain region which then gives rise to a larger Ie degradation. Moreover, the developed profiling technique can be used as a good monitor of the antenna effect caused by the plasma charging induced damage. Acknowledgments This work was supported by the National Science Council, Taiwan, under contract N SC89 -22 I S E00g-4 S.

A New Observation of the Reverse Short Channel Effect in Submicron n-MOSFET by Using Gate-Induced Drain Leakage Current Measurement

In this paper, a significant channel length dependence of the drain leakage current and is degradation is investigated for the first time in submicron n-MOSFETs. This phenomenon is attributed to the increase of lateral nonuniform channel doping concentration near the source/ drain sides as a result of the process-induced boron redistribution effecr It is visible for devices with increasing channel doping near the source/drain sides due to oxidation-enhanced diffusion (OED) or process-induced implant damages as the channel length decreases. A simple band-oband tunneling model and numerical simulation are used to verify this channel length dependent behavior.