E. Vilella

Crosstalk-Free Single Photon Avalanche Photodiodes Located in a Shared Well

Advances in single photon avalanche detector (SPAD) arrays propose improving the fill factor by confining several SPADs in the same well, with a main issue related to crosstalk. In applications that measure at fixed times, the pixels can be inhibited before the arrival of the crosstalk charge. This letter reports the crosstalk characterization in an array of SPADs, where the sensors share the same n-well (fill factor 67%), and fabricated in a conventional CMOS technology. The reduction of the gating time completely eliminates the crosstalk, as predicted by the theory and TCAD simulations.

Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article.

Readout electronics for low dark count pixel detectors based on Geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

High sensitivity and excellent timing accuracy of the Geiger mode avalanche photodiodes make them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase in the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 mm and a high integration 0.13 mm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

Readout electronics for low dark count Geiger mode avalanche photodiodes fabricated in conventional HV-CMOS technologies for future linear colliders

This work presents low noise readout circuits for silicon pixel detectors based on Geiger mode avalanche photodiodes. Geiger mode avalanche photodiodes offer a high intrinsic gain as well as an excellent timing accuracy. In addition, they can be compatible with standard CMOS technologies. However, they suffer from a high intrinsic noise, which induces false counts indistinguishable from real events and represents an increase of the readout electronics area to store the false counts. We have developed new front-end electronic circuitry for Geiger mode avalanche photodiodes in a conventional 0.35 μm HV-CMOS technology based on a gated mode of operation that allows low noise operation. The performance of the pixel detector is triggered and synchronized with the particle beam thanks to the gated acquisition. The circuits allow low reverse bias overvoltage operation which also improves the noise figures. Experimental characterization of the fabricated front-end circuit is presented in this work.

Dynamic range extension of SiPM detectors with the time-gated operation

The silicon photomultiplier (SiPM) is a novel detector technology that has undergone a fast development in the last few years, owing to its single-photon resolution and ultra-fast response time. However, the typical high dark count rates of the sensor may prevent the detection of low intensity radiation fluxes. In this article, the time-gated operation with short active periods in the nanosecond range is proposed as a solution to reduce the number of cells fired due to noise and thus increase the dynamic range. The technique is aimed at application fields that function under a trigger command, such as gated fluorescence lifetime imaging microscopy.

Geiger-Mode Avalanche Photodiodes in Standard CMOS Technologies

Photodiodes are the simplest but most versatile semiconductor optoelectronic devices. They can be used for direct detection of light, of soft X and gamma rays, and of particles such as electrons or neutrons. For many years, the sensors of choice for most research and industrial applications needing photon counting or timing have been vacuum-based devices such as Photo-Multiplier Tubes, PMT, and Micro-Channel Plates, MCP (Renker, 2004). Although these photodetectors provide good sensitivity, noise and timing characteristics, they still suffer from limitations owing to their large power consumption, high operation voltages and sensitivity to magnetic fields, as well as they are still bulky, fragile and expensive. New approaches to high-sensitivity imagers tend to use CCD cameras coupled with either MCP Image Intensifiers, I-CCDs, or Electron Multipliers, EM-CCDs (Dussault & Hoess, 2004), but they still have limited performances in extreme time-resolved measurements.

Avoiding sensor blindness in Geiger mode avalanche photodiode arrays fabricated in a conventional CMOS process

The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology

The present article describes the design of a new low-voltage radiation-tolerant band gap reference circuit. The proposed circuit has been designed for biasing analog modules in the slow control of the Data Handling Processor for reading DEPFET sensors in the Super KEK-B particle accelerator in Japan. It has been implemented in a 90nm standard CMOS technology. The BGR circuit provides a sub-1V voltage reference. It is possible to operate the circuit with 1 and 1.2V supplies. For that, a trimming net based on resistors was included. Tolerance to radiation is achieved by means of enclosed layout transistors and guard rings. The total area of the BGR is 181x110μm2. The power consumption is set at 18.70uA for the 1V supply case and at 55.18uA for the 1.2V supply case.

Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments

An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purpose the H35DEMO, a large area HV-CMOS demonstrator chip, was designed by KIT, IFAE and University of Liverpool, and produced in AMS 350 nm CMOS technology. It consists of four pixel matrices and additional test structures. Two of the matrices include amplifiers and discriminator stages and are thus designed to be operated as monolithic detectors. In these devices the signal is mainly produced by charge drift in a small depleted volume obtained by applying a bias voltage of the order of 100V. Moreover, to enhance the radiation hardness of the chip, this technology allows to enclose the electronics in the same deep N-WELLs which are also used as collecting electrodes. In this contribution the characterisation of H35DEMO chips and results of the very first beam test measurements of the monolithic CMOS matrices with high energetic pions at CERN SPS will be presented.

Dynamic range extension of a SPAD imager using non-uniformity correction techniques

The extraordinary sensitivity of single-photon avalanche diodes (SPADs) makes these devices the ideal option for vision systems aimed at low-light applications. Nevertheless, there exist large dark count rate and photon detection probability non-uniformities, which reduce the dynamic range of the detector. As a result, the capability to create image contrast is severely damaged or even lost. This paper presents the implementation of a correction algorithm to compensate for the mentioned non-uniformities and thus extend the contrast of the generated images. To demonstrate its efficiency, the proposed technique is applied to real images obtained with a fabricated SPAD image sensor. An increase of more than 3 b of contrast is obtained.