E. Vincent

Review on high-k dielectrics reliability issues

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

A thorough investigation of MOSFETs NBTI degradation

An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.

Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature

Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<inf>BS</inf>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<inf>GS</inf>, V<inf>DS</inf> (V<inf>BS</inf>) conditions as a single I<inf>DS</inf> lifetime dependence is observed with V<inf>GD</inf> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<inf>DS</inf>) and multi vibrational excitation (higher I<inf>DS</inf>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<inf>BS</inf> = −V<inf>DD</inf> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<inf>BS</inf> = −V<inf>DD</inf>/2 for design reliability.

MIM capacitance variation under electrical stress

Abstract Due to strong requirement in term of capacitance voltage linearity, MIM capacitance stability during the whole operating lifetime of the product appears to be a key issue to warrant the reliability of this device. Using a constant current stress, two effects can be noticed on the evolution of the stressed C–V characteristics: a voltage shift to negative bias and a significant increase of the capacitance. Both phenomena have been demonstrated to be strongly correlated and to have the same origin: the trapped charges in oxide, which can generate new dipoles in the dielectric and, as a result, modulate the dielectric permittivity.

Wear-out, breakdown occurrence and failure detection in 18–25 Å ultrathin oxides

Abstract In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented. For sub-25 A, Hard BD is no longer hard. A complete description of the novel failure manifestation (progressive breakdown) is done. Associated wear-out is modelled and a physical mechanism is proposed. Finally, the relevance of the failure definition is discussed. It is a crucial point, to adopt a rigorous methodology for reliability prediction. It is concluded that, in the case of progressive breakdown, noise occurrence must be considered as the relevant time to failure.

Quasi-breakdown in ultra-thin SiO/sub 2/ films: occurrence characterization and reliability assessment methodology

This paper discusses different statistical approaches for the quasi-breakdown phenomenon. In particular, a novel methodology based on the idea that breakdown and quasi-breakdown are competing mechanisms and that they have to be separately analyzed, is developed and well validated for oxide thickness ranging from 3.5 down to 2.5 nm. This methodology is demonstrated to well explain all the quasi-breakdown rate variations with temperature, voltage, area and oxide thickness. Moreover, this new approach enables to rigorously determine the quasi-breakdown acceleration factor with temperature and electric field, which have been found to be different from the breakdown ones. As a result, and confirmed by the difference observed between the obtained time to breakdown and time to quasi-breakdown spreads, the defects at the origin of both phenomena have to be different. Finally, a reliability assessment methodology is presented enabling a proper analysis of both phenomena for reliability evaluation and lifetime prediction.

Dielectric reliability in deep-submicron technologies: From thin to ultrathin oxides

Abstract This paper focuses on the dielectric reliability in the thin and ultrathin oxide regime. The wear-out mechanisms and the breakdown phenomena related to the Si SiO 2 system are considered within the 12nm-5nm oxide thickness range. The degeneration evolution with respect to the oxide thickness and the consequences of the mechanisms involved in the various failure modes which limit the dielectric reliability are discussed.

Design-in-Reliability Approach for NBTI and Hot-Carrier Degradations in Advanced Nodes

A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.

Designing in reliability in advanced CMOS technologies

Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper presents selected topics relevant to realize an efficient design-in reliability methodology in the latest generation CMOS technologies. NBTI is discussed in terms of characterization using On-The-Fly (OTF) methodology. Extension of OTF method is discussed using bias patterns to gain insights into NBTI under analog operation. A reliability simulation methodology is discussed against requirements for optimization and integration within an existing design flow. The features of this methodology are illustrated using some simple design examples.

Generalized trapping kinetic model for the oxide degradation after Fowler–Nordheim uniform gate stress

The practicality of modeling the power law degradation observed in thin dielectrics after Fowler–Nordheim stress has been demonstrated on the basis of a generalized trapping approach with appropriate trap cross-section and density profiles. A detailed mathematical analysis of the negative bulk oxide charge kinetics has been established using incomplete Gamma and generalized hypergeometric functions, after assuming exponentially varying trap cross-section and density profiles throughout the oxide. These spatial distributions could be due to the structural nature of the oxide after growth. Moreover, the asymmetry of the charge distribution centroid for negative and positive gate bias stress has been satisfactorily interpreted by neglecting the trapping in the tunneling region near the cathode. Overall this generalized kinetic trapping model provides very good fitting of the variation of the trapped oxide charge with the injection dose for oxide thicknesses between 5.5 and 10 nm. The evolution of the charge ...