D. Goguenheim

Octadecyltrichlorosilane monolayers as ultrathin gate insulating films in metal-insulator-semiconductor devices

In order to fabricate metal‐insulator‐semiconductor (MIS) devices with gate insulating films thinner than 5.0 nm, organic monolayers have been grafted on the native oxide layer of silicon wafers. We demonstrate that a single monolayer of octadecyltrichlorosilane with a 2.8 nm thickness allows to fabricate a silicon based MIS device with gate current density as low as 10−8 A/cm2 at 5.8 MV/cm, insulator charge density lower than 1010 cm−2, fast interface state density of the order of 1011 cm−2 eV−1, and dielectric breakdown field as high as 12 MV/cm. Moreover, this insulating film is thermally stable up to 450 °C.

Theoretical and experimental aspects of the thermal dependence of electron capture coefficients

The thermal activation of the capture coefficient c is very often treated in a semiclassical way, resulting from a simple energy barrier. Experimentally, this activation energy Eb is said to be the slope of ln[c(T)] vs 1/T kT. Unfortunately, many experimental evidences deny this analysis and suggest that a single energy barrier is not enough to reproduce the physical behavior of a point defect. Here we propose a more complete approach to the problem of nonradiative carrier capture assisted by phonons, which is based on a less restrictive hypothesis and leads to a compact formulation of the capture coefficient. This formula reproduces the previous asymptotic forms at high temperature in the strong coupling limit, but remains valid over the whole temperature range and for any strength of the coupling between the lattice and the defect. This point is illustrated for typical cases and the accuracy of the new formula is shown in the case of the so‐called B level in GaAs, whose capture coefficient does exhibit ...

New insights on the electronic properties of the trivalent silicon defects at oxidized 〈100〉 silicon surfaces

We perform a deep level transient spectroscopy (DLTS) measurement of the band‐gap energy distribution of the trivalent silicon defects (Pb centers) on as‐oxidized 〈100〉 silicon wafers. By comparison with the 〈111〉 silicon surface, we isolate the energy distribution of the Pb1 center. Its acceptor level is found at 0.42 ± 0.02 eV from the conduction band while the acceptor level for the 〈100〉 Pb0 center is found at 0.22 ± 0.01 eV, a value smaller than at the 〈111〉 surface (0.33 ± 0.01 eV). We obtain new results about the capture cross sections of the 〈100〉Pb centers by energy‐resolved DLTS trap filling experiments. The electron capture cross section of 〈100〉Pb1 is determined for the first time (5×10−16 cm2), while the electron capture cross section for 〈100〉 Pb0 (8×10−15 cm2) is found to be in agreement with earlier results.

Microstructure and resistance switching in NiO binary oxide films obtained from Ni oxidation

Oxide Resistive Random Access Memories (OxRRAM) are discussed for future high density non volatile memory chips. NiO and other simple binary transition metal oxides (such as TiO2, HfO2 or ZrO2) have recently attracted much attention. In most cases, polycrystalline oxide films are deposited by reactive sputtering on conductive substrates to form bi-stable Metal/Resistive oxide/Metal (MRM) structures. In this paper, an alternative way is explored to obtain NiO films from the controlled oxidation of a Ni metallic film. Different thermal treatments were evaluated to oxidize the metallic film with conditions preventing the complete consumption of Ni film used as bottom electrode. Process parameters of Rapid Thermal Annealing (RTA) route were adjusted to achieve controlled oxidation. Microstructural and electrical analyzes were performed to apprehend the influence of the process parameters on the switching behavior. Reproducible resistive switching phenomena have been demonstrated in Pt/NiO/Ni structures with threshold voltage varying from 2 to 5 V depending on oxidizing conditions.

Accurate measurements of capture cross sections of semiconductor insulator interface states by a trap‐filling experiment: The charge‐potential feedback effect

A measurement technique and analysis are presented for the accurate determination of the capture cross sections of the interface states in metal‐oxide‐semiconductor (MOS) structures. The technique utilizes the interface‐trap‐filling kinetics during measurements by energy‐resolved deep level transient spectroscopy (DLTS). High accuracy is attained by accounting in the analysis for the charge‐potential feedback effect which is a unique feature of the MOS structure and which presents a critical difficulty in the DLTS measurement of capture cross sections in MOS devices. The accurate measurement of the capture cross sections obtained in this work allows us to study several electronic properties of the Si‐SiO2 interface including (i) the behavior of the capture cross sections of interface states created by high‐field stress on MOS devices, and (ii) the determination of the capture cross section of dangling bonds at the 〈100〉‐oriented Si‐SiO2 interface. Finally, the possibility of determining the degeneracy fac...

Nature of the defects generated by electric field stress at the Si-SiO2 interface

We have characterized the density of states, the capture cross sections, and the annealing properties of the Si‐SiO2 interface defects generated during electron injection under high electric field stress. These properties are compared to those of the interface states present in as‐oxidized Si‐SiO2 structures which are known to be due primarily to the trivalent silicon defects (Pb centers), the main intrinsic defects on thermally oxidized silicon. Although the energetic distribution of the state densities and the annealing properties are similar, we found that the capture cross sections are strongly different. This leads to the conclusion that the interface defects generated by high electric field stress are not strictly identical to Pb centers, but probably ‘‘Pb‐like’’ defects. A possible model is discussed.

Degradation and recovery of polarization under synchrotron x rays in SrBi2Ta2O9 ferroelectric capacitors

Elementary Pt∕SrBi2Ta2O9∕Pt ferroelectric capacitors have been structurally characterized by x-ray diffraction using highly brilliant synchrotron radiation. A microstructural analysis of the stacked layers was performed from the collection of high-quality one-dimensional and two-dimensional diffraction patterns. During x-ray diffraction experiments, peculiar electrical behaviors under irradiation were evidenced. Indeed, depending upon their initial state (poled or nonpoled), the capacitors have exhibited drastic changes in their electrical characteristics after or under irradiation, both “fatiguelike” (polarization reduction) and∕or “imprintlike” (voltage shift) phenomena being observed. Using a sample environment specially designed to measure in situ the evolutions of ferroelectric characteristics, the kinetics of both degradation and restoration of ferroelectric properties of the SrBi2Ta2O9-based capacitors under x-ray radiation have been analyzed. Reduction and recovery of switchable polarization have ...

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25‐125 8C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. DiAerent degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what eAectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 8C using inverter and pass transistor operations in a 0.35 mm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation. # 1999 Elsevier Science Ltd. All rights reserved.

Hot-carrier to cold-carrier device lifetime modeling with temperature for low power 40nm Si-bulk NMOS and PMOS FETs

The persistence of hot-carrier degradation down to low voltages is analyzed in recent CMOS nodes through the effect of multivibration excitation (MVE) of the Si-H bonds and deexcitation by multiphonon emission. This new mechanism is described by an energy framework and originates from the channel current density independently of voltage and geometry. MVE mode is enhanced with temperature in NMOS and PMOS devices due to its strong coupling to the lattice disregarding the negative bias contribution in PMOS.

Influence of various process steps on the reliability of PMOSFETs submitted to negative bias temperature instabilities

Abstract In this paper, we analyze the impact of various process steps on the reliability of PMOSFET’s submitted to Negative Bias Temperature Instabilities stress conditions. We give some evidence of the complete thermal anneal of interface states induced by NBTI and investigate the influence of the oxide thickness and of the final forming gas anneal. Then we show a NBTI lifetime improvement after a fluorine implant through the gate and an arsenic bulk doping value increase.