A. Bravaix

On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's

We propose a new methodology to characterize the negative bias temperature instability (NBTI) degradation without inherent recovery. The extracted parameters are the linear drain current, the threshold voltage and the transconductance. We compare the new and the usual methodologies and show a logarithmic time dependence of both the degradation and the recovery. The hole trapping (detrapping) is directly correlated to the V/sub T/ degradation (recovery), and plays the main role in the NBTI in ultra-thin gate-oxide PMOSFETs.

A thorough investigation of MOSFETs NBTI degradation

An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.

Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature

Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<inf>BS</inf>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<inf>GS</inf>, V<inf>DS</inf> (V<inf>BS</inf>) conditions as a single I<inf>DS</inf> lifetime dependence is observed with V<inf>GD</inf> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<inf>DS</inf>) and multi vibrational excitation (higher I<inf>DS</inf>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<inf>BS</inf> = −V<inf>DD</inf> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<inf>BS</inf> = −V<inf>DD</inf>/2 for design reliability.

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.

The Energy-Driven Hot-Carrier Degradation Modes of nMOSFETs

In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron-electron scattering become the dominant contribution to the degradation. Finally, for even lower energy, multiple vibrational excitation mechanism starts taking the lead.

General framework about defect creation at the Si∕SiO2 interface

This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si∕SiO2 interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows one to physically model the reliability of metal oxide semiconductor field effect transistors, and particularly negative bias temperature instability permanent part, and channel hot carrier to cold carrier damage.

CMOS device design-in reliability approach in advanced nodes

a general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation

BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset

This paper presents understandings on BTI variability based upon an extensive dataset. This enables to select between various theoretical statistical models and to propose a novel description approach for the NBTI-induced mismatch for different technological nodes and a comparison with time-zero variability. The impact from transistor to gate level is also evaluated.

New Insights into Recovery Characteristics Post NBTI Stress

In this work, we investigate recovery characteristics post NBTI stress when the recovery bias remains negative but lower in magnitude than the stress bias, consolidating the viewpoint involving role of hole trapping during NBTI degradation. We show that successive negative recovery biases can be applied to view trapping and detrapping behavior explicitly

Design-in-Reliability Approach for NBTI and Hot-Carrier Degradations in Advanced Nodes

A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.