Eamon Hynes

Development and characterisation of a surface micromachined FET pressure sensor on a CMOS process

Abstract This paper presents the development methodology and performance results of a surface micromachined FET pressure sensor integrated into a CMOS process. The working pressure range examined is 15 to 95 psi of absolute pressure. The sensor consists of a polysilicon pillbox structure which forms an evacuated cavity. The polysilicon is the gate electrode of an MOS device created using the cavity as the gate dielectric, deflection of the polysilicon with applied pressure can be sensed as a change in drain current of this MOS device. The finite-element program ANSYS is used to establish suitable values for the area and thickness of the diaphragm and the cavity height. A device simulator is used to predict the performance of the MOS structure for various deflections. The fabrication of the sensor element takes place after the source/drain anneal and before interlayer deposition of an otherwise standard CMOS process. The output current of a fabricated MOS sensor with diaphragm plate length of 75 μm over the range of 15 to 95 psi increased from 70 to 170 μA at a bias of V ds =11 V, V gs =13 V.

Verification of 2-D MEMS model using optical profiling techniques

This paper describes the application of scanning white light interferometry to profile single layer and multilayer, surface micromachined, micromechanical elements. The measured profile data is used to verify a 2-D finite difference model of device deflection under pressure and electrostatic forces. Devices modelled include pressure sensors, switches and process characterisation structures. The model is designed to include effects such as non-rigid structure supports and stress gradients through the structure. The optical profiling is used to quantify the significance and deflection shape resulting from these effects. The optical profiling has been compared with the AFM profiling and some comparisons are made between these methods. r 2001 Elsevier Science Ltd. All rights reserved.

Determination of the effect of processing steps on the CMOS compatibility of a surface micromachined pressure sensor

A surface micromachining process for the fabrication of a pressure sensitive field effect transistor (FET), compatible with complementary metal oxide semiconductor (CMOS) processing, has been established in which residual membrane stress can be tuned without changing the underlying CMOS operation. The residual membrane stress must be controlled at a low tensile value for optimum operation of the pressure FET. Controlling this residual stress involves the development of suitable processing conditions, and the effect of alteration from standard CMOS processing on the underlying circuitry must be evaluated. The effects of different processing conditions for a surface micromachined polysilicon pressure sensing membrane on the CMOS characteristics are presented. Variations in the polysilicon sensor layer deposition and implant conditions in the surface micromachining process and back-end CMOS interlayer dielectric reflow were examined as these strongly influence the residual stress in the membrane. The electrical characteristics for devices that had only CMOS processing did not vary significantly from the electrical characteristics of devices that had the pressure sensor surface micromachining layer processing.

Wafer level inspection for determination of yield of surface-micromachined pressure sensors

Development of a surface micromachining process for commercial scale production of absolute pressure sensors necessitates the definition of inspection tests at each stage of the process and for the completed packaged product. The yield measurement described in this paper is for a Field Effect Transistor pressure sensor integrated into a CMOS process. This measurement can be divided into verification of the electrical and mechanical properties of the pressure device. This paper describes the development of a simple method for mechanical yield determination. The method is based on a visual inspection procedure where the interference rings observed under a conventional 5X/20X inspection microscope, are correlated with white light interferometry (wafer level and packaged devices) and Atomic Force Microscopy (AFM) (wafer level) measurements. The application of these two profiling methods is also compared in the paper. Based on this work a simple, low cost, automatic system for yield determination using standard equipment can be developed. Initial results from a software system for inspection automation are presented.