M. O'Neill

An investigation of on-chip spiral inductors on a 0.6 /spl mu/m BiCMOS technology for RF applications

Inductors are very important passive elements in many RF circuit applications. Integrated on-chip metal inductors, formed in conventional CMOS or BiCMOS technologies, suffer from performance limitations due to substrate injection through the oxide, metal resistive losses, and substrate losses due to low-resistivity substrates. These problems mean that the highest attainable inductor quality factor (Q) is significantly lower than that which can be attained from off-chip inductors. This paper details an analysis of on-chip metal inductors fabricated on a 0.6 /spl mu/m BiCMOS technology. Issues relating to test structure layout, measurement techniques, inductor composition, and inductor characterization and modeling are addressed. In addition, an analysis of the impact of inductor shape and metal thickness on inductor performance is examined.

A diaphragm based piezoelectric AlN film quality test structure

Aluminum nitride (AlN) is becoming a commonly used piezoelectric material for various applications due to its compatibility with CMOS processing. However, the piezoelectric properties of AlN are highly dependent on the deposition process and the underlying layers, and typically require several test structures in order to determine the quality of the film. This paper highlights a MEMS based diaphragm test structure which allows various types of material characterization to be tested, in order to determine the quality of the AlN film on a bulk micromachined device wafer.

CMOS compatible low-frequency aluminium nitride MEMS piezoelectric energy harvesting device

Piezoelectric materials are widely used in various applications including sensors, actuators, and energy harvesting devices. Energy harvesting devices can be used to power autonomous wireless sensors that are placed in remote or difficult to reach areas, where replacing a battery is not practical or feasible. In this paper the authors present work on the fabrication and design of a CMOS compatible Aluminium Nitride (AlN) piezoelectric based MEMS cantilever structure for harvesting vibrational energy. In order for AlN to be piezoelectric it needs to be highly structured in the c-axis (002) crystal orientation. The deposition of highly structured AlN and its polarity is dependent on the underlying films and their crystal orientation. XRD rocking curve results from this paper show a highly oriented (002) AlN film with a FWHM value of 2.1°. The MEMS cantilever structures were fabricated using standard MEMS fabrication techniques using SOI wafers. By optimising the AlN material deposition process and the stress values in the cantilever structures the authors were able obtain a power density of 2.55 mW/ cm3/g2 for a single MEMS structure with 500 nm thick AlN. The cantilever structure had a resonant frequency of approximately 150 Hz. In this paper the authors also investigated methods to increase the bandwidth of the cantilever structures, by building an array of devices with slightly varying length masses.

Frequency response of variants of a cantilever beam

The increasing importance of autonomous devices has focused on strategies of energy harvesting in order to provide the required energy for these kinds of applications. One of the possibilities to develop energy harvesting is through piezoelectric materials which can convert mechanical vibrations into electrical energy. An examination of finite element modeling of cantilever beams is discussed here and the advantages and future possibilities for fabrication are investigated. This paper highlights how researchers can create different shapes or fabrication techniques to optimize the resonant frequency based on finite element modeling.

Characterization and modeling of LDMOS transistors on a 0.6 /spl mu/m CMOS technology

High voltage integrated circuits (HVICs) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used high voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). The LDMOS transistor is based on the lightly doped drain concept. Two of the main objectives in designing LDMOS devices are to minimize the on-resistance while still maintaining a high breakdown voltage. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel into this region. This lightly doped drain region can have a large effect on the on-resistance, saturation current and feedback capacitance of the device. This paper presents a LDMOS device, considers some of the key specific parameters related to LDMOS devices, discusses a sub-circuit SPICE model implemented to model the LDMOS characteristics and investigates some interconnect metallization effects.

The CAP-FET, a scaleable MEMS sensor technology on CMOS with programmable floating gate

A new MEMS sensor architecture is presented that converts mechanical displacement of a conductive diaphragm directly to a current. The electrical bias on the mechanical element is capacitively coupled to an electrically floating MOS gate that controls the sensor output current. The sensor is manufactured using a process module that slots directly in to a CMOS process. Both the sensor architecture and process module will scale with shrinking CMOS generations. Injection of charge onto the floating gate can be used to program the sensor threshold voltage. The sensor architecture has been demonstrated as a pressure sensor on a CMOS process.

Location Dependence of a MEMS Electromagnetic Transducer with respect to an AC Power Source

A MEMS, silicon based device with a piezoelectric layer and an integrated magnet is presented for magnetic to electrical transduction. The cantilever structure can be configured either as an energy harvester to harvest power from an AC power line or as an AC current sensor. The positioning of the transducer with respect to the AC conductor is critical in both scenarios. For the energy scavenger, correct positioning is required to optimize the harvested power. For the current sensor, it is necessary to optimise the sensitivity of the sensor. This paper considers the effect of the relative position of the transducer with respect to the wire on the resulting electromagnetic forces and torques driving the device. It is shown here that the magnetic torque acting on a cantilever beam with an integrated magnet and in the vicinity of an alternating electromagnetic field is a very significant driver of the cantilever oscillations.

Optimisation of integrated RF varactors on a 0.35 /spl mu/m BiCMOS technology

Integrated varactors are becoming a common feature for many RF designs and in particular RF voltage controlled oscillators (VCOs). Optimisation of the quality of both the inductor and the varactor from the VCO core is essential. This work details the characterisation and optimisation of a number of varactor types available on a typical sub-micron BiCMOS process. Engineering of the bottom plate of the varactor was used to optimise the quality factor of the varactor. No additional mask layers or processing steps were required to achieve this. Integrated isolated diode varactors with quality factors of 30 at 2 GHz have been demonstrated with tuning capacitance ranges of 2.5. Integrated MOS capacitor varactors with quality factors of 50 at 2 GHz have been demonstrated with tuning capacitance range of 5.

Prediction of AC performance of double-polysilicon bipolar transistors from e-test parameters: An experiment

AC characterisation of silicon bipolar and BiCMOS processes for RF applications is necessary because of the ever-increasing operating speed of bipolar devices. The data acquisition parameter extraction steps associated with AC characterisation and modelling are time consuming and tedious and cannot easily be implemented as part of standard process monitor measurements. This paper discusses a methodology for relating the readily available e-test parameter database to the AC parameters which are more difficult to obtain. The work was done on a 0.6 /spl mu/m BiCMOS process which is suited to mixed mode RF chip designs.