Eamon O'malley

A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz

This paper describes the implementation of a novel and highly versatile digital pulse width modulator (DPWM) -probably the most critical component in any digitally controlled switching power converter. Its new architecture, composed of a delay-locked loop (DLL) and programmable DPWM module, allows the generation of high resolution, high switching frequency (f/sub m/) PWM signals. The DPWM IC was designed using a standard 0.35-/spl mu/m CMOS process and supports switching frequencies beyond 15 MHz.

A 16-bit fixed-point digital signal processor for digital power converter control

This paper describes a novel and highly versatile reduced instruction set (RISC) based fixed-point digital signal processor (DSP). Its architecture, instruction set, and integrated programmable digital pulse width modulator (DPWM) have been optimized for digitally controlled switched mode power converters (SMPCs). Designed using the Verilog hardware description language (HDL), the prototype DSP integrated circuit (IC) was built on a standard 0.35 mum digital CMOS process (with a 20 K gate count). It occupies less then 1.5 mm2 and dissipates approximately 5 mW from a 3.3 V supply at 50 MIPs. The device provides a programmable and cost effective solution for digitally controlled SMPCs

A novel digital single-wire quasi-democratic stress share scheme for paralleled switching converters

A novel Digital Stress Share (DSS) scheme, useful for paralleled switch-mode power converters (SMPCs), is presented. Due to its unique feature set DSS lends itself particularly well to modern power architectures where load currents (or — more generically — converter stresses) need to be actively balanced between an arbitrary number of digitally controlled DC-DC switching converters. The DSS scheme is suitable for single-wire implementation offering a low-cost and robust platform. DSS is master-less and quasi-democratic, eliminating all known drawbacks of analog current share lines, and offering significant improvements over competing digital current share methods. It features inter-device stress share communication with fully predictable timing, regardless of the number of SMPCs working in parallel. Data throughput as well as data storage requirements are minimized. Measurement results confirm excellent stress share performance under various operating conditions. The DSS scheme is versatile, robust, fault-tolerant and scalable. DSS defines an electrical bus interface, as well as an isochronous protocol.

Masterless multirate control of parallel DC-DC converters

This paper introduces a new masterless multirate control scheme for current share in DC-DC converters. Comprising of a multirate digital controller, decoupling interactions between control loops, a single wire digital communication bus, facilitating simple and reliable communication between devices, and a modular current share architecture. Results show excellent static and dynamic current matching, and have been commercially proven.

Digital control scheme for robust clock tuning and PWM phase synchronization in digitally controlled multi-POL applications

This paper describes a novel clock tuning and subsequent PWM phase synchronization scheme for digitally controlled switching power converters. Its architecture and circuit blocks are presented and explained in detail. The scheme has been implemented in a commercially available digital controller integrated circuit (IC) using a standard CMOS process. Experimental results from a multi point-of-load (POL) application are presented.