Karl Rinne

Magnetics on silicon: an enabling technology for power supply on chip

Data from the ITRS2003 roadmap for 2010 predicts voltages for microprocessors in hand-held electronics will decrease to 0.8V with current and power increasing to 4A and 3W, respectively. Consequently, low power converters will move to multimegahertz frequencies with a resulting reduction in capacitor and inductor values by factors of 5 and 20, respectively. Values required at 10 MHz, for a low power buck converter, are estimated at 130 nH and 0.6 uF, compatible with the integration of magnetics onto silicon and the concept of power supply-on-chip (PSOC). A review of magnetics-on-silicon shows that inductance values of 20 to 40nH/mm/sup 2/ can be achieved for winding resistances less than 1/spl Omega/. A 1-/spl mu/H inductance can be achieved at 5 MHz with dc resistance of 1/spl Omega/ and a Q of four. Thin film magnetic materials, compatible with semiconductor processing, offer power loss density that is lower than ferrite by a factor of 5 at 10 MHz. Other data reported includes, lowest dc resistance values of 120 m/spl Omega/ for an inductance of 120 nH; highest Q of 15 for an inductance of 350 nH and a current of 1 A for a 1- /spl mu/H inductor. Future technology challenges include reducing losses using high resistivity, laminated magnetic materials, and increasing current carrying capability using high aspect-ratio, electroplated copper conductors. Compatible technologies are available in the power switch, control, and packaging space. Integrated capacitor technology is still a long-term challenge with maximum reported values of 400 nF/cm/sup 2/.

A review of planar magnetic techniques and technologies

This paper presents an extensive survey of techniques and technologies used to implement planar magnetic structures in modern DC to DC converters. The survey emphasises the practical applications of these devices. The trends are analyzed in the context of the marketplace and some predictions of future direction are attempted.

A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz

This paper describes the implementation of a novel and highly versatile digital pulse width modulator (DPWM) -probably the most critical component in any digitally controlled switching power converter. Its new architecture, composed of a delay-locked loop (DLL) and programmable DPWM module, allows the generation of high resolution, high switching frequency (f/sub m/) PWM signals. The DPWM IC was designed using a standard 0.35-/spl mu/m CMOS process and supports switching frequencies beyond 15 MHz.

A self-compensating adaptive digital regulator for switching converters based on linear prediction

This paper presents a self-compensating adaptive digital regulator applied to dc to dc converters. Implementing linear prediction, it adapts online, and may be operated continuously, characterizing disturbances in the loop, allowing optimal disturbance rejection. A dual purpose controller-predictor provides robust performance in low complexity hardware.

Sensorless current-mode control of a digital dead-beat DC-DC converter

A digital current-mode controller for dc-dc converters is introduced. The current-mode loop is sensorless, relying on constants and internal loop states; removing the need to sense controlled voltages or currents for the inner loop. Furthermore, a fast current-mode control mechanism is implemented by utilizing dead-beat control. The resulting controller is robust and surprisingly uncomplicated. It is well suited to VLSI integration in a low geometry process. An interesting aspect of this control scheme is that it facilitates the application of a low resolution PWM.

High Resolution DPWM in a DC-DC Converter Application Using Digital Sigma-Delta Techniques

This paper demonstrates a DC-DC converter application in which a multi-bit digital sigma-delta modulator pre-processes the duty-cycle value before application to the DPWM, increasing the effective resolution of the DPWM dramatically. In this method, the DPWM duty-cycle command is pre-processed by a multi-bit digital sigma-delta modulator, so that the DPWM quantization noise is shaped in frequency. As a result, the total quantization noise at the output of the DC-DC converter is reduced, and the effective resolution of the DPWM in the control loop is increased dramatically. A prototype converter was seen to perform with an effective DPWM resolution of at least 11 bits, with an actual DPWM resolution of less than 6 bits

Control of dc-dc converters by direct pole placement and adaptive feedforward gain adjustment

A direct pole-placement control strategy is introduced, and applied in the design of a buck type, dc-dc converter. The solution involves a feedforward component in the control strategy, to eliminate steady-state errors. The value of the feedforward gain, which completely eliminates steady-state error, is dependant upon the gain of the plant, which may not be known exactly. In this design the feedforward gain is determined adaptively, so as to drive the steady state error to zero

Digital control law using a novel load current estimator principle for improved transient response

A method for the early detection of load transients using a current estimator for VR applications is presented. This technique combined with a new charge-balanced digital control law can improve the dynamic response to fast load transients. The key advantage of this new approach is the early detection of load transients which is independent of ADC sampling, where most existing solutions incorporate relatively expensive, complex and energy consuming high-speed ADCs. The presented method significantly reduces the inherent delay associated with fixed sampling detection in the control loop. The load current estimation during transient is critical for improved transient performance and allows the possibility of using a charge-balanced control law. Unlike existing algorithms, the presented control law is capable of implementing non-zero load lines required for VRMs. A full description of this control law is detailed. The current estimator technique and the charge-balanced digital control law are critically assessed using Matlab/Simulink. The resulting transient behaviour gives a significant improvement over conventional control schemes.

A 16-bit fixed-point digital signal processor for digital power converter control

This paper describes a novel and highly versatile reduced instruction set (RISC) based fixed-point digital signal processor (DSP). Its architecture, instruction set, and integrated programmable digital pulse width modulator (DPWM) have been optimized for digitally controlled switched mode power converters (SMPCs). Designed using the Verilog hardware description language (HDL), the prototype DSP integrated circuit (IC) was built on a standard 0.35 mum digital CMOS process (with a 20 K gate count). It occupies less then 1.5 mm2 and dissipates approximately 5 mW from a 3.3 V supply at 50 MIPs. The device provides a programmable and cost effective solution for digitally controlled SMPCs

Efficiency-Based Current Distribution Scheme for Scalable Digital Power Converters

The trend in next-generation switched-mode power supplies will lead to modular, scalable solutions, which deliver power efficiently over a wide range of operation. This paper details a new approach to introduce more advanced control features to improve system efficiency into these scalable solutions. While these methods have been incorporated into multiphase converters in the past, they all require the distribution of information among the individual converters. An advantage of the proposed method is that it does not require such communication signals between the individual power supplies and is, therefore, fully scalable and cost effective. A system comprising individual, smart converters is proposed, where each converter regulates its respective output power to a level with high efficiency. Converters not required for the delivered output power are shut down. The proposed approach is analyzed theoretically. Implementation details for a field-programmable gate array experimental prototype system are given. The system performance for a four-converter prototype system is analyzed and discussed. The efficiency obtained is compared with the efficiency of a multiphase system with phase-shedding operation and the efficiency of a system with independent power converters without phase-shedding support.