Anthony Kelly

Digital control law using a novel load current estimator principle for improved transient response

A method for the early detection of load transients using a current estimator for VR applications is presented. This technique combined with a new charge-balanced digital control law can improve the dynamic response to fast load transients. The key advantage of this new approach is the early detection of load transients which is independent of ADC sampling, where most existing solutions incorporate relatively expensive, complex and energy consuming high-speed ADCs. The presented method significantly reduces the inherent delay associated with fixed sampling detection in the control loop. The load current estimation during transient is critical for improved transient performance and allows the possibility of using a charge-balanced control law. Unlike existing algorithms, the presented control law is capable of implementing non-zero load lines required for VRMs. A full description of this control law is detailed. The current estimator technique and the charge-balanced digital control law are critically assessed using Matlab/Simulink. The resulting transient behaviour gives a significant improvement over conventional control schemes.

A novel digital single-wire quasi-democratic stress share scheme for paralleled switching converters

A novel Digital Stress Share (DSS) scheme, useful for paralleled switch-mode power converters (SMPCs), is presented. Due to its unique feature set DSS lends itself particularly well to modern power architectures where load currents (or — more generically — converter stresses) need to be actively balanced between an arbitrary number of digitally controlled DC-DC switching converters. The DSS scheme is suitable for single-wire implementation offering a low-cost and robust platform. DSS is master-less and quasi-democratic, eliminating all known drawbacks of analog current share lines, and offering significant improvements over competing digital current share methods. It features inter-device stress share communication with fully predictable timing, regardless of the number of SMPCs working in parallel. Data throughput as well as data storage requirements are minimized. Measurement results confirm excellent stress share performance under various operating conditions. The DSS scheme is versatile, robust, fault-tolerant and scalable. DSS defines an electrical bus interface, as well as an isochronous protocol.

Masterless multirate control of parallel DC-DC converters

This paper introduces a new masterless multirate control scheme for current share in DC-DC converters. Comprising of a multirate digital controller, decoupling interactions between control loops, a single wire digital communication bus, facilitating simple and reliable communication between devices, and a modular current share architecture. Results show excellent static and dynamic current matching, and have been commercially proven.

Automated optimization of generalized model predictive control for DC-DC converters

Generalized predictive control (GPC) offers a method of designing digital compensators directly in the discrete-time domain. In this paper, an automatic design process based on the optimization of a few GPC parameters is presented. The application to DC-DC converters offers real benefits because of its clearly defined design process, time-domain performance criteria, simple tuning technique and guarantee of stability. For practical applications, the guarantee of stability may not be sufficient, certain performance criteria must also be achieved. In this design process, a performance index is used in the optimization routine to quantify specific performance objectives. A novel performance index is presented which weights performance and robustness for a more optimized compensator design. For illustration purposes an optimal GPC compensator is designed and tested for a buck converter. The resulting compensator is critically assessed in simulation and validated with experimental hardware.

Current share in multiphase SMPCs by digital filtering

This paper introduces a new method of passive current balancing for digital control based upon the duty-cycle matching principle. The method does not rely on a current balancing loop and therefore the stability and performance concerns associated with the traditional current balance loop are obviated. Being sensorless, it is insensitive to current measurement inaccuracies caused by noise, component value tolerance or variation. It will be shown that effective current balancing can be achieved via some simple modifications to standard voltage mode control laws, allowing current balancing to be achieved with minor additional complexity.

Controller scalability methods for digital Point Of Load converters

Unmodeled dynamics cause DC-DC controller design to be an iterative procedure where controller parameters are tuned and re-tuned to achieve the desired transient performance. Once the controller is designed any change of the output filter requires a new compensator design to guarantee stable operation. In this paper programmability of controller parameters in digital Point Of Load (POL) converters is exploited to investigate methods to scale an existing controller to accommodate variation of the resonant frequency of the LC filter, with the aim to eliminate the need for such iterative tuning. A new method to scale a compensator is then proposed to maintain bandwidth and phase margin of the original controller design. Experimental results are provided for 12-to-1.2V, 20A, 500kHz 0.18μm CMOS digital POL converter to show the effectiveness of the proposed method.

Digital control scheme for robust clock tuning and PWM phase synchronization in digitally controlled multi-POL applications

This paper describes a novel clock tuning and subsequent PWM phase synchronization scheme for digitally controlled switching power converters. Its architecture and circuit blocks are presented and explained in detail. The scheme has been implemented in a commercially available digital controller integrated circuit (IC) using a standard CMOS process. Experimental results from a multi point-of-load (POL) application are presented.