Nadya Belova

Multichip reticle approach for OPC model verification

The complexity of current semiconductor technology due to shrinking feature sizes causes more and more engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is the reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, the reticle expenses have become even more critical. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 0.13 technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified the low volume reticle (LVR) approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing litho and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments.

Advances in spherical harmonic device modeling: calibration and nanoscale electron dynamics

Improvements in the Spherical Harmonic (SH) method for solving Boltzmann Transport Equation (BTE) are presented. The simulation results provide the same physical detail as analytical band Monte Carlo (MC) calculations, and are obtained approximately a thousand times faster. A new physical model for surface scattering has also been developed. As a result, the SHBTE model achieves calibration for a complete process of I-V characteristics and substrate current consistently for the first time.

Simple method for restricting OPC model minimum spacing and width for a no failure imaging solution

Optical proximity correction (OPC) procedure for modifying designs requires an OPC setting effectively accounting for manufacturing and imaging constraints. Reticle-writing and imaging tool capabilities drive the choice for the minimum feature of an OPC model. Aggressiveness of an optical proximity correction is determined by a discretization setting for an OPC algorithm. Some OPC scheme parameters are there to restrict the minimum spacing and width to avoid circuit failures. The OPC minimum spacing parameter controls bridging lines. The OPC minimum width parameter limits the correction of trenches responsible for circuit breakdown. An aggressive choice of minimum spacing and width for an OPC setting can results in circuit failure: shortage or breakdown. The conservative approach results in poor circuit performance. The methodology was deployed at LSI Logic Corporation for empirical optimization of the OPC minimum spacing/width settings for a no failure imaging solution of OPCed masks. The proposed procedure is particularly beneficial for dark field metal interconnect masks. The approach was successfully validated for 130nm and 90nm backend technology metal layers.

Statistical simulation, calibration and analysis of 0.25 CMOS technology

A statistical simulation flow for the characterization and analysis of 0.25 CMOS technology is presented. The simulation tools PDFAB, Tsuprem4 and Medici were used in this work. The simulation tools were calibrated to the Etest data and their capability to predict were verified. The statistical input parameters were collected from actual manufacturing distributions. Simulation results showed very good agreement with the manufacturing data.

Statistical analysis of poly line printability affected by sPSM manufacturing errors

LSI Logics OPC package, Molotof, integrated into several RET flows has been successfully applied for strong phase shift mask simulation and optimization. Molotof simulator was used to predict sPSM imaging performance in response to statistical errors of alternating phase shift reticle manufacturing. Mask manufacturing errors were reproduced by generating a virtual gds mask with random values of sPSM control parameters such as phase depth, phase width and phase intensity. By measuring critical dimensions and image placement errors of a simulated aerial image for each random event, the image printability performance was calculated. The approach allows for quantitative evaluation and optimization of a strong PSM manufacturing specification by analyzing the distributions of critical dimensions and image placement errors. 2D-model, metrology and simulation flow for performing statistical analysis are discussed. Sensitivity to a single parameter variation and full statistical analysis of the 90nm poly line imaging performance affected by manufacturing errors is presented. The optimum range of phase depth, phase width and phase intensity, yielded 100% of critical dimensions and image placement errors, complying with 90nm technology design rules was found in simulation. Simulation results are confirmed by empirical data.

Sensitivity of the 65-nm poly line printability to sPSM manufacturing errors

A methodology and a Monte Carlo simulation flow with integrated LSI Logics OPC package, Molotof, was applied to the 65nm poly line sensitivity analysis. Strong phase shift mask (sPSM) manufacturing specifications were optimized to obtain image critical dimensions (CD) and image placement errors (IPE) complying with technology design rules. Reticle manufacturing statistical errors of phase depth, phase width, and phase intensity imbalance were used to generate a virtual sPSM for imaging poly lines. A criterion for qualifying reticle specification is to obtain all latent image CDs and IPEs within a design rule allowed range for a given mask specification. The approach allows for computing reticle and litho budgets into CD imaging performance. We present simulation and empirical results of statistical analysis of the 65nm poly line (clear field) printability, and a method for optimizing a strong phase shift reticle specification. Sensitivity to a single parameter variation and full statistical analysis of the 65nm poly line imaging performance affected by manufacturing errors is presented. The optimum reticle specification, yielded 100% of critical dimensions and image placement errors, was found in simulation and confirmed by empirical data.

Best/worst case extraction and yield cost estimation using Monte Carlo statistical analysis

Methodology and simulation results from Monte Carlo sensitivity analysis based on discretization of the second-order Taylor expansion for electrical device characteristics are presented. The same dice conditions for both NMOS and PMOS were modeled. Non-degenerate distributions of electrical parameters were formed. Results of selected direct process/device simulation were mapped onto distributions obtained by the Monte Carlo analysis. The resultant distributions were used to establish yield cost associated with desired best/worst case electrical characteristics. The approach was tested for two technologies and showed excellent agreement with available experimental statistical data.

Extension of Spherical Harmonic Method to RF Transient Regime

The space and time dependent electron Boltzmann transport equation (BTE) is solved self-consistently with the Poisson and transient hole current-continuity equation. A transient Spherical Harmonic expansion method is used to solve the BTE. By this method we can efficiently solve the BTE in the RF regime to observe how the complete distribution function responds to a rapid transient. Calculations on a BJT, which give the time dependent distribution function over a large energy range 0–3eV, throughout the device, as well as average quantities, require only 40 minutes CPU time on an Alpha workstation.