Eddy De Greef

Memory size reduction through storage order optimization for embedded parallel multimedia applications

Abstract In this paper, we present novel strategies that are capable of significantly reducing the required memory sizes for a large class of data-intensive multimedia applications. The size reduction is obtained by reusing memory locations for arrays as much as possible through optimization of the storage order. These strategies are equally well suited for parallel and mono-processing applications, and are particularly useful in an embedded application context, where memory size is usually one of the main cost factors. Their feasibility and effectiveness is demonstrated by experimental results for some real-life multimedia applications, for which a considerable size reduction has been obtained.

A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms

The key characteristic of next generation embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The embedded system designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.

Memory Allocation and Assignment

In embedded systems the memory architecture can be more or less freely chosen. Different choices can lead to solutions with a very different cost, which means that it is important to make the right choice. Therefore, we have introduced a memory allocation and assignment step in our design flow, where trade-offs are made to arrive to an optimal memory architecture. In this step we take into account both the bandwidth constraints defined in chapter 10, and the target implementation technology.

Cost Models and Estimation

This chapter provides an overview of the cost models in terms of size, area, band-width, and power, as used in this book. In practice, timing issues are addressed as constraints and the cost function is mainly composed of area and power related terms. For memories, it is usually feasible to obtain closed-form formulas for the area and power in terms of the main parameters: number of bits, number of words, postdecoding (folding) factor, number of ports (R, W and RAV). Of course this model will heavily depend on the type of memory: SRAM, DRAM, SDRAM, Pointer-Addressed Memory, Video-RAM and so on. The parameters are not accurately available in each step of the DTSE methodology but they can always be estimated, albeit only crudely in the early steps.

Geometrical Program Modeling

This chapter describes the geometrical data- and control-flow modeling techniques for data-dominated applications. The literature on this topic is very scattered, and many different formalisms are being used. We present a unified view on these techniques and formalisms. Next, we show how these models can be used and extended to accurately describe the occupation of memories used for storing multi-dimensional data. Moreover, we derive the necessary and sufficient constraints that have to be satisfied by the design parameters (i.e. execution and storage order) in order to arrive at a valid algorithm implementation (either in hardware or in software). The optimization techniques presented in the subsequent chapters are all partly based on the models presented here, wherever they have to manipulate or analyse the loop nest code and the array signals.

Polyhedral Data-Flow Analysis for Data Storage and Transfer Exploration

This chapter describes a theoretical polyhedral basis for data-flow analysis of multi-dimensional signal processing algorithms, especially in the context of DTSE. As mentioned in chapter 1, a data-flow analysis operating with groups of scalars is necessary in order to handle realistic RMSP applications. Formally, these groups are represented by images of polyhedra and are noted as basic sets further on. They can be used to identify useful signal partitions for almost all other DTSE steps but the actual decision on which partitions to withhold depends on the step and on the actual application at hand. The results also have to be carefully evaluated because in some cases the partitioning can lead to an explosion into small basic sets which are too fine grain for an acceptable solution complexity of our steps.

Global Transformation Strategies for Power and Storage Size Reduction

In this chapter, the main focus will be on global transformations which improve the original code in terms of DTSE related cost factors. First, data-flow transformations will be considered in section 8.1 to section 8.3. They allow to remove redundant access in the data-flow and they serve as enablerfor the subsequent transformation steps by removing data-flow bottle-necks wherever it is cost effective to do so.

Specification Issues and Pruning Strategies

In this chapter, several issues concerning input specification representation and preprocessing steps for the actual DTSE methodology will be briefly discussed. These issues become much more complex when applied to practical designs, but in the scope of the book they cannot be presented in more detail.

Data Transfer and Storage Exploration Methodology

In this chapter, our DTSE methodology is introduced and illustrated on a simple but representative real-life application. The starting point of the DTSE methodology [58, 59] is a system specification with accesses on multi-dimensional (M-D) signals which can be statically ordered (single thread of control). The output is a net-list of memories and address generators (see figure 1.7), combined with a transformed specification where the background memory accesses are heavily reorganized. This new code is the input for the architecture (high-level) synthesis when custom realizations are envisioned, or for the software compilation stage in the case of predefined processors.

Related Work on Data Transfer and Storage Management

In this chapter, an extensive summary is provided of the main related work in the domain of this book. It is organized in a hierarchical way where the most important topics receive a separate discussion, with pointers to the available literature. Wherever needed, a further subdivision in subsections or paragraphs is made.