Sven Wuytack

Minimizing the required memory bandwidth in VLSI system realizations

In this paper, we present the problem of storage bandwidth optimization (SBO) in VLSI system realizations. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The importance and the effect of SBO is shown on realistic examples both in the video and asynchronous transfer-mode (ATM) domains. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. Our problem formulation leads to the optimization of a conflict (hyper) graph. For the target domain of ATM, only flat graphs without loops have to be treated. For this subproblem, a prototype tool has been implemented to demonstrate the feasibility of automating this important system design step.

Formalized methodology for data reuse exploration in hierarchical memory mappings

Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data dominated applications. In the past, this task has been identified as crucial in a complete low-power memory management methodology. But effective formalized techniques to deal with this specific task have not been addressed yet. In this paper the design freedom available for the basic problem is explored in-depth and the outline of a systematic solution methodology is proposed. The efficiency of the methodology is illustrated on a real-life motion estimation application.

Memory management for embedded network applications

In embedded network applications, typically a very large part of the area cost is due to memory units. Also the power for such applications is heavily dominated by the storage and transfers. Given its importance, we have developed a systematic memory management methodology in which the storage related issues are optimized as a first step. In this paper, we present our methodology for embedded network applications. It includes both a dynamic memory management stage, where the data types and virtual memory managers are defined, and a physical memory management stage, where the custom memory architecture is defined. As demonstrated on an industrial example, the application of the methodology results in a heavily power and/or area optimized custom memory architecture for a given application.

Fast and extensive system-level memory exploration for ATM applications

A memory architecture exploration methodology and CAD techniques for network protocol applications are presented. Prototype tools have been implemented, and applied on part of an industrial ATM application to show how our novel approach can be used to easily and thoroughly explore the memory organization search space at the system level. An extended, novel method for signal to memory assignment is proposed which takes into account memory access conflict constraints. The number of conflicts are first optimized by our flow graph balancing technique. Significant power and area savings were obtained by performing the exploration thoroughly at each of the degrees of freedom in the global search space.

Flow graph balancing for minimizing the required memory bandwidth

In this paper we present the problem of flow graph balancing for minimizing the required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The effect of flow graph balancing is shown on an example. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. This leads to the optimization of a conflict graph.

Code transformations for data transfer and storage exploration preprocessing in multimedia processors

Platform-independent source code transformations can greatly help alleviate the data-transfer and storage bottleneck. This article covers global data-flow, loop, and data-reuse-related transformations, and discusses their effect on data transfer and storage, processor partitioning, and parallelization.

Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer

Matisse is a design flow intended for developing embedded systems characterized by tight interaction between control and data-flow behavior, intensive data storage and transfer, dynamic creation of data, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip HW/SW implementation. Matisse supports stepwise system-level exploration and refinement, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for HW synthesis, SW compilation, and HW/SW interprocessor communication synthesis. Application of Matisse on telecom protocol processing systems shows significant improvements in area usage and power consumption.

Matisse: a system-on-chip design methodology emphasizing dynamic memory management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.

Transforming set data types to power optimal data structures

In this paper, we present a novel approach to model the search space for the custom implementation of set data types, a data type that is commonly found in important application domains such as network component realizations and database applications. The main objective is to arrive at power efficient realizations of these data types in custom data structures, but the model can also be used with nonpower cost functions. Based on the model, we propose an efficient optimization method for finding the implementation with minimum power consumption without performing an exhaustive scan of the search space. The range of power costs for different solutions can easily span four orders of magnitude, so a near optimal solution is crucial. This paper also strongly contributes to our overall goal of a higher level of specification and shorter design cycles for table-based memory organizations for applications where these data types are frequently used. The proposed model and methodology are suited for both hardware and software realizations.

Exploring parallelizations of applications for MPSoC platforms using MPA

This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a multi-processor platform architecture. By specifying the parallelization at a high abstraction level, and leaving the actual source code transformations to the tool, a designer can try out many parallelizations in a short time. A parallelization may use either functional or data-level splits, or a combination of both. An accompanying high-level simulator provides rapid feedback about the expected performance of a parallelization, based on platform parameters and profiling data of the sequential application on the target processor. The use of the tool and simulator are demonstrated on an MPEG-4 video encoder application and two different platform architectures.