Frank Franssen

Automating High Level Control F'low Transformations For Dsp Memory Management

A method and a prototype tool for performing high level control flow transformations for DSP memory management are presented in this paper. Their efficacy is demonstrated by applying them to an industrial regularity detection algorithm, leading to an optimized storage scheme for the large multi-dimensional (M-D) signals within the algorithm. The data flow and control flow of the algorithm are captured by a Polyhedral Dependency Graph. This model has been designed to efficiently capture M-D data flows with a complexity that is independent from size parameters [10, 11]. Using this model, traditional loop-transformations can be generalized and captured in a control flow transformation technique that is amenable to analytical optimization. Performance figures of a CAD tool implementing the transformation method demonstrate the feasibility of this approach for the envisaged application domain.

TRANSFORMATION OF NESTED LOOPS WITH MODULO INDEXING TO AFFINE RECURRENCES

For multi-dimensional (M-D) signal and data processing systems, transformation of algorithmic specifications is a major instrument both in code optimization and code generation for parallelizing compilers and in control flow optimization as a preprocessor for architecture synthesis. State-of-the-art transformation techniques are limited to affine index expressions. This is however not sufficient for many important applications in image, speech and numerical processing. In this paper, a novel transformation method is introduced, oriented to the subclass of algorithm specifications that contains modulo expressions of affine functions to index M-D signals. The method employs extensively the concept of Hermite normal form. The transformation method can be carried out in polynomial time, applying only integer arithmetic.

Memory and Data-Path Mapping for Image and Video Applications

In this chapter, we will present a high-level synthesis methodology that is particularly suited for irregular high-throughput subsystems realized on an application-specific architecture. This Cathedral-3 methodology is targeted to real-time signal processing applications with a low potential for time multiplexing, as occurring, for example, in image and video applications. The most crucial steps in this methodology are supported by appropriate synthesis techniques embedded in prototype tools. The emphasis lies on high-level synthesis supporting the dominant design cost factors, i.e., an area-efficient memory organization and a customized data-path configuration, both within the stringent throughput requirements. The power of the approach will be illustrated with realistic demonstrators.

Modeling Data Flow and Control Flow for DSP System Synthesis

A data flow and control flow model is presented for use in high level synthesis of efficient time multiplexed architectures targeted towards real-time DSP systems. The model is an extension to the polyhedral models used in array synthesis techniques. The model features a mathematical description of dependencies between individual operations and signal instances of multi-dimensional signals for algorithms that can be described by Conditional Affine Recurrence Equations. It allows for a generalization of high level control flow transformations and their steering by efficacious optimization methods. The inherent amenity of this type of model for these tasks is motivated by examples. Important tasks in high level synthesis that can exploit this model are memory management for time multiplexed architectures and non-linear transformations for array architectures, but also other tasks may benefit. The former task will be described in more detail in this paper.