Edgar Albuquerque

The Clear-PEM Electronics System

The Clear-PEM detector system is a compact positron emission mammography scanner with about 12000 channels aiming at high sensitivity and good spatial resolution. Front-end, Trigger, and Data Acquisition electronics are crucial components of this system. The on-detector front-end is implemented as a data-driven synchronous system that identifies and selects the analog signals whose energy is above a predefined threshold. The off-detector trigger logic uses digitized front-end data streams to compute pulse amplitudes and timing. Based on this information it generates a coincidence trigger signal that is used to initiate the conditioning and transfer of the relevant data to the data acquisition computer. To minimize dead-time, the data acquisition electronics makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system operates at 100-MHz clock frequency, and is capable of sustaining a data acquisition rate of 1 million events per second with an efficiency above 95%, at a total single photon background rate of 10 MHz. The basic component of the front-end system is a low-noise amplifier-multiplexer chip presently under development. The off-detector system is designed around a dual-bus crate backplane for fast intercommunication between the system boards. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates. Monte Carlo simulation results evaluating the trigger performance, as well as results of hardware simulations are presented, showing the correctness of the design and the implementation approach

A new low-noise logic family for mixed-signal integrated circuits

A new low-noise logic family is presented in which the supply current spikes due to switching are much reduced with respect to conventional CMOS circuits. A comparison with existing alternative circuits shows that, for the same supply voltage and the same power consumption, the new circuits have smaller area, higher noise margins, and lower delay.

Evaluation of substrate noise in CMOS and low-noise logic cells

The substrate noise generated by conventional CMOS and by different low-noise logic families is investigated by computer simulation of the circuits extracted from the layouts including the resistive substrate model. A widely used 0.8 /spl mu/m CMOS technology is considered. It is found that, in small cells, the noise reduction with respect to CMOS is only significant in cells with complementary outputs. In large driver cells, considerable noise reduction can be obtained (without complementary outputs). One of the low-noise families, however, exhibits large noise for high supply wire inductance (in the examples here, with 2 V supply voltage, the noise is even higher than for CMOS cells, for inductance above 10 nH).

Current-balanced logic for mixed-signal IC's

We present a new low-noise family, Current-Balanced Logic (CBL), suitable for use in low-power/low-voltage, high-resolution, mixed-signal integrated circuits. The noise performance of the proposed circuits is similar to that of the best previously reported circuits, but the new circuits are simpler and faster, have lower power dissipation and wider noise margins, and use a smaller area.

An overview of the Clear-PEM breast imaging scanner

We present an overview of the Clear-PEM breast imaging scanner. Clear-PEM is a unique dual-head Positron Emission Mammography scanner using APD-based detector modules that are capable of measuring depth-of-interaction (DOI) with a resolution of 2 mm in 20 mm long LYSO:Ce crystals. Such capability leads to an image spatial resolution of 1.2 mm and a high efficiency, foreseeing the detection of 3 mm breast lesions in less than 7 minutes exams. The full system comprises 192 detector modules in a total of 6144 LYSO:Ce crystals and 384 32-pixel APD arrays readout by ASICs with 192 input channels that represents an unprecedented level of integration in PET systems. Throughout the project and besides the detector module, we had developed dedicated Frontend and Data Acquisition electronics, the mechanical design and construction of the detector heads and the robotic gantry, as well as all the software that include calibration (energy, time and DOI), normalization and image reconstruction algorithms. In this work we will discuss the developments and present the commissioning results of the detector before the beginning of the clinical trials program, scheduled for the end of the present year.

Characterization of the Clear-PEM breast imaging scanner performance

We present results on the characterization of the Clear-PEM breast imaging scanner. Clear-PEM is a dual-head Positron Emission Mammography scanner using APD-based detector modules that are capable of measuring depth-of-interaction (DOI) with a resolution of 2 mm in LYSO:Ce crystals. The full system comprises 192 detector modules in a total of 6144 LYSO:Ce crystals and 384 32-pixel APD arrays readout by ASICs with 192 input channels, which represents an unprecedented level of integration in APD-based PET systems. The system includes Frontend and Data Acquisition electronics and a robotic gantry for detector placement and rotation. The software implements calibration (energy, time and DOI), normalization and image reconstruction algorithms. In this work, the scanner main technical characteristics, calibration strategies and the spectrometric performance in a clinical environment are presented. Images obtained with point sources and extended uniform sources are also presented. The first commissioning results show 99.7% active channels. After calibration, the dispersion of the channels absolute gain is 15.3%, which demonstrate that despite the large number of channels the system is rather uniform. The mean energy resolution at 511 keV is 15.9% for all channels, and the mean DOI constant is 5.9%/mm, which is consistent with a 2 mm DOI resolution, or better. The coincidence time resolution at 511 keV, for a energy window between 400 and 600 keV, is 5.2 ns FWHM. The image resolution measured with point sources was found to be of the order of 1.3 mm FWHM. The DOI capability was found to have a strong impact on the image sharpness. Images of extended uniform 68Ge sources, corrected for sensitivity and for the artifacts due detector dead spaces, have good uniformity. First clinical breast images are presented.

A comparative study of low-noise logic cells for mixed mode integrated circuits

The two basic low-noise logic families are CSL, which is the best known, and the recently proposed CBL. In this paper we present the first experimental evaluation of the CBL family, which provides good agreement with the theoretical predictions. We perform a comparative study of the two families supported by measurements on a test chip. This shows (among other conclusions) that most CBL circuits have significantly lower area and slightly lower delay than CSL circuits, for the same static power consumption; however, for very low power levels (slow performance), CSL circuits may have lower area and delay.

First experimental results with the Clear-PEM detector

First experimental results of the imaging system Clear-PEM for positron emission mammography, under development within the framework of the Crystal Clear Collaboration at CERN, are presented. The quality control procedures of crystal pixels, APD arrays and assembled detector modules are described. The detector module performance was characterized in detail. Results on measurements of light yield, energy resolution, depth-of-interaction and inter-channel cross-talk are discussed. The status of the development of the front-end electronics and of the data acquisition boards is reported.

An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuits

Two logic families, CSL (Current-Steering Logic) and CBL (Current-Balanced Logic), that have been proposed to reduce the substrate noise in mixed-signal integrated circuits, are compared with conventional CMOS by measurements on a test chip. Large CBL cells with wire bonding have a reduction of the substrate noise effect, with respect to CMOS, by a factor of 2.5, whereas CSL is noisier than CMOS. This agrees with the simulations. The moderate noise improvement shown in the simulations by CBL circuits with complementary outputs is not confirmed experimentally. The results here show that previous evaluations based on the amplitude of the supply current spikes are unsuitable to assess the real noise performance.