Kevin Harer

A robust solution to the timing convergence problem in high-performance design

Traditional ASIC design flows have treated logic synthesis and physical design as separate steps in the flow. A recent trend in design automation has been to integrate placement and logic synthesis operations for designs that strive for high performance. The motivation for this is ascribed to achieving timing convergence. These efforts attempt a brute-force combination of techniques from the two fields. We present an architecture for combining synthesis transforms with rough placement. There are three main contributions of this paper. First we present a system architecture that permits a clean separation of placement and synthesis issues and combines the two solutions in an elegant manner. Second, we propose a minor modification to the current ASIC design flow to enable timing convergence. Third, we use design rules for correct circuit operation to drive the placement and the synthesis components of the system. We present results for a set of high performance ASIC designs which demonstrate the practicality of our method.

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent

With the growing complexity and gradually shrinking power requirements in the system-on-chip designs, sophisticated global power management policies (which orchestrate the switching between power states of multiple power domains) are commonplace. Recent research has paved some novel ways to verify the sophisticated on-chip architectural power management decisions and analyze the verification coverage. However, one of the primary challenges in verifying such power management architectures stems from the mixed implementation of such strategies, where the local power controllers are in hardware and the global power management is implemented in software/firmware. There has been lack of effort to build a unified and automated framework for power intent verification and coverage analysis for generic power management logics. This paper tries to develop an end-to-end automated framework enabled by a tool named POWER-TRUCTOR for power intent validation.

Supporting sequential assumptions in hybrid verification

We present a method for using a set of temporal properties (SVA, PSL, OVA, RTL monitors) as environment models for industrial-strength hybrid verification that combines formal methods with constrained random simulation. We demonstrate the effectiveness of the method on real-world designs.

Formal methods for coverage analysis of architectural power states in power-managed designs

The architectural power intent of a design defines the intended global power states of a power-managed integrated circuit. Verification of the implementation of power management logic involves the task of checking whether only the intended power states are reached. Typically, the number of global power states reachable by the global power management strategy is significantly lesser than the possible number of global power states. In this paper, we present a formal method for determining the set of reachable global power states in a power-managed design. Our approach demonstrates how this task can be further constrained as required by the verification engineer. We highlight the efficacy of the proposed methods over several test-cases.

Learning from Constraints for Formal Property Checking

Constraints are commonly used in both simulation and formal verification in order to specify expected input conditions and state transitions. Constraint solving is a process to determine input vectors which satisfy the set of constraints during constrained random simulation. Even though constraints are used in formal property checking to restrict the search space, constraint solving has never had direct application to formal property checking. There are often many simple, yet powerful, invariants that can be learned from constraint solving during constrained random simulation. These invariants are shown in this paper to significantly simplify the formal verification problem. We use approximate constraint solving to compute an approximate set of valid input vectors. The approximate set of valid input vectors are a strict superset of the set of all legal input vectors. We use BDD techniques to compute these input vectors during constrained random simulation, then process the resulting BDDs for learning invariants which can be used during formal property checking. This paper presents efficient BDD algorithms to learn invariants from the BDDs generated from approximate constraint solving. We also present how these learned invariants can be applied to the formal property checking. Experimental results show that invariants learned during constraint solving can significantly improve the performance of formal property checking with many industrial designs.

Learning from constraints for formal property checking

Constraints are commonly used in both simulation and formal verification in order to specify expected input conditions and state transitions. Constraint solving is a process to determine input vectors which satisfy the set of constraints during constrained random simulation. Even though constraints are used in formal property checking to restrict the search space, constraint solving has never had direct application to formal property checking. There are often many simple, yet powerful, invariants that can be learned from constraint solving during constrained random simulation. These invariants are shown in this paper to significantly simplify the formal verification problem. We use approximate constraint solving to compute an approximate set of valid input vectors. The approximate set of valid input vectors are a strict superset of the set of all legal input vectors. We use BDD techniques to compute these input vectors during constrained random simulation, then process the resulting BDDs for learning invariants which can be used during formal property checking. This paper presents efficient BDD algorithms to learn invariants from the BDDs generated from approximate constraint solving. We also present how these learned invariants can be applied to the formal property checking. Experimental results show that invariants learned during constraint solving can significantly improve the performance of formal property checking with many industrial designs.