Kaushik De

RSYN: a system for automated synthesis of reliable multilevel circuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN. >

Defect isolation using scan-path testing and electron beam probing in multi-level high density asics

Electron beam probing is a powerful technique for analyzing functional failures in integrated circuits. A common approach used for isolating defects is to trace a bad signal on a failing pin through the circuit. The inputs and outputs of each logical node can be compared against simulated results to determine functionality. This method has several limitations which are discussed in this paper -- most notably, it is often an extremely time consuming process. Scan- path designs have been introduced which increase the observability and controllability of internal circuit nodes. The use of ASIC scan-path architecture is increasing due to the improved testability compared to non-scan designs. Scan-path architecture also offers opportunities for more efficient failure analysis of functional failures. In this paper we present a successful method of defect isolation using scan-path testing in conjunction with electron beam probing. Using this method, a fault area or node is identified using a test datalog, and the defect is precisely located using an electron beam probe station. This paper discusses in detail the integration of scan testing with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements.

Failure analysis for full-scan circuits

We present a complete system for failure analysis of full-scan circuits. A novel scheme has been proposed to handle multiple faults up to a certain extent by ranking the faults according to the likelihood of being present in the defective part. The user can interactively recompute the suspect fault list by changing some parameters. If the suspect fault list is large, we generate new test patterns to distinguish the faults in the suspect list. User can iterate over a defective part several times until the suspect fault list is reasonably small. Then each suspect site is probed using E-beam. This tool is integrated into design environment of LSI Logic Corporation and produced good results when applied on a few industry circuits.

Test methodology for embedded cores which protects intellectual property

Testing of embedded cores poses a great challenge. These cores cannot be tested in isolation because core I/Os are not directly accessible from ASIC I/Os. A novel test methodology is developed which generates a partial netlist for protection of intellectual property (IP) by performing structural analysis. This partial netlist is used in ASIC level test generation. For the remaining gates of the core, patterns are supplied to test those gates, which can be applied through only core scan chain. Another scheme is developed to select a few I/Os optimally to add boundary scan circuits to improve IP protection.

ProperSYN: A portable parallel algorithm for logic synthesis

An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.<<ETX>>

Reliability driven logic synthesis of multilevel circuits

Two schemes for reliability-driven logic synthesis of multilevel circuits are presented. Previous schemes of duplications required 100% area overhead. The first scheme uses the Berger code for concurrent error detection for the multilevel circuits. The average area overhead is 22% in this scheme. The second scheme uses the output partitioning and parity prediction method. It is found that the average area overhead of this scheme is about 67%.<<ETX>>

A portable parallel algorithm for logic synthesis using transduction

Combinational logic synthesis is a very important phase of VLSI system design. But the logic synthesis process requires large computing times if near optimal quality of the logic network is desired. Parallel processing is fast becoming an attractive solution to reduce the computational time. Recently, researchers have started to investigate parallel algorithms for problems in logic synthesis and verification. Much of the work in parallel algorithms for CAD reported to date, however, suffers from a major limitation. The parallel algorithms proposed for the CAD applications are designed with a specific underlying parallel architecture in mind. Moreover, incompatibilities in programming environments also make it difficult to port these programs across different parallel machines. As a result, a parallel algorithm needs to be developed afresh for every target parallel architecture. The ongoing project of ProperCAD offers an attractive solution to that problem. It allows the development and implementation of a parallel algorithm on the CHARM runtime system such that it can be executed in all the parallel machines without any change in the program. In this paper, we describe a portable parallel algorithm for logic synthesis based on the Transduction method, called ProperSYN. This algorithm uses an asynchronous message driven data-flow model of computation, with no explicit synchronizing barriers separating different phases of parallel computation as used in many previously developed parallel algorithms. Our algorithm is therefore more scalable to large numbers of processors. The algorithm has been implemented and it runs on a variety of parallel machines. We present results on several benchmark circuits for shared memory MIMD machines like Sequent Symmetry and Encore Multimax, distributed memory MIMD machine like the Intel/860 hypercube and distributed processing systems like networks of SUN workstations. >

Parallel Logic Synthesis Using Partitioning

In this paper, we present a partitioning approach of parallel logic synthesis, which is different from the previous approaches which involved parallelization of individual operations within the synthesis algorithm. We partition the given logic circuits and distribute the partitions to different processors for synthesis. For good load balancing, partitioning algorithm is tuned so that the estimated synthesis times of individual partitions are equal. To improve the quality of synthesized circuits, we propose a novel iterative repartitioning and resynthesis approach to parallel logic synthesis. Experimental evaluation in several large circuits are shown on a network of workstations, and results are compared with MIS.

Can test length be reduced during synthesis process

Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-at faults in the circuit. The length of a test set affects the test application cost. The synthesis process has been modified to obtain circuits that can be tested with smaller test length. Results of the implementation have shown significant reduction in test length with little increase in run time over the MIS-II synthesis system and very little increase in literal count.<<ETX>>

A Shared Memory Parallel Algorithm for Logic Synthesis

The Transduction Method [9] has been shown t o be a powerful tool in the optimization of multi-level networks. However, this algorithm takes large execution times, making these tools dificult t o use for large networks. In this paper, we present a parallel algorithm for logic synthesis based on the Transduction Method that is suitable for execution on a sharedmemory multiprocessor. This implementation, called Parallel TRANSduction (PTRANS), also uses partitioning to break up large networks and performs interand intra-partition dynamic load balancing. We report experimental results on an 8-processor Encore multiprocessor for various benchmark networks.