Bradley McCredie

Modeling, measurement, and simulation of simultaneous switching noise

The computer package designer depends on modeling power supply noises to ensure that system designs will function properly. Power supply noises can have a tremendous effect on system operation and performance. The circuit simulation of a system power distribution is very challenging since it requires accurate models of active devices, passive components, transmission lines, and a very large power distribution network. This paper presents the development of a high-frequency power distribution model for the simulation of simultaneous switching noise of a complementary metal-oxide-semiconductor (CMOS) chip on a multilayered ceramic substrate. Measurements are performed on a CMOS chip with simultaneously switching off-chip drivers (OCDs). The modeling approach is validated by the excellent agreement between the measurement waveforms and simulation results.

Design of the Power6 Microprocessor

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

The clock distribution of the POWER4 microprocessor

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.

Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor

The POWER6trade is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-k copper interconnects. Chips with split- and connected-core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each. On-chip noise measurements are compared to simulation. The noise measurements and simulation both show that the shorted core power grid design has less noise and a higher maximum frequency.

Long lossy lines (L/sup 3/) and their impact upon large chip performance

The semiconductor industry expects the performance of microprocessors to continue at its current rate of improvement; i.e. clock rates should double every two to three years. This is a commendable goal but it is also fair to question whether this is an achievable goal. The fundamental problem is that as groundrules are reduced, the natural tendency is to make smaller conductor cross-sectional areas. The result is a high resistance line that exhibits slow wave propagation effects. This reduces the general performance expectations. As circuits become faster and denser on the chip, line delays become greater than expected. This problem is analyzed and potential chip and packaging solutions are offered. Clock rate predictions for various design and process options are made. A tactical recommendation to consider a total packaged electronics solution is presented.

Power distribution modelling of high performance first level computer packages

A methodology for obtaining a model of the power distribution of a computer package is presented. This model is suitable for determining the noise and aiding in the design of a computer package. The physical features of a typical first-level multi-layered computer package is shown. Semiconductor chips and decoupling capacitors are placed on the top surface of the package and the module is connected to a board or card for communication with other components of the computer. A schematic of the final inductance model of a multi-layered ceramic single chip module used in computer products is shown.<<ETX>>

Performance effects of switching noise on CMOS microprocessors

The simultaneous switching noise of off-chip drivers and internal circuits affect the performance of the CMOS chips. These effects are quantified using voltage waveforms obtained from simulations on a high-frequency package model.

Determination of of operating frequency and signal integrity of various implementations of a symmetric multiprocessor computer

The primary function of the package designer is to determine the maximum frequency of operation and functionality of a given computer design point. Determination of the maximum operating frequency requires calculation of both off chip driver and receiver delays as well as package and interconnect delays. Determination of signal integrity is generally a noise analysis problem, that requires calculation of the total noise from all possible sources at the input to an off chip receiver. This paper outlines the analysis methodology and techniques used to determine the performance and functionality of various implementations of a common symmetric multiprocessor computer architecture.

A model to hardware comparison of simultaneous switching noise on a CMOS chip

The simultaneous switching noise simulation and the comparison of those simulations to laboratory measurements of noise on a specially designed CMOS test chip on a multilayer ceramic SCM are presented.

Simultaneous switching noise measurement on a CMOS chip on an MLC SCM

The characterization of the simultaneous switching noise magnitude of 0.25 /spl mu/m channel CMOS drivers obtained through high-frequency measurements is presented in this paper.