Edward Sanchez

Minority carrier diffusion length measurements in 6H–SiC

Minority carrier diffusion lengths were measured as a function of temperature and position along the growth axis of lightly nitrogen doped boules of 6H–SiC grown by the physical vapor transport technique. It is shown that the diffusion lengths increase from 1to2microns in the seed portion of the boule to about 4microns in the tail portion of the boules. Deep levels transient spectroscopy measurements revealed the presence of deep electron traps with the activation energies of 0.35eV, 0.5eV, 0.65eV, and 1eV. The densities of all these traps decrease when moving from seed to tail of the boules. A good correlation between the change of the lifetime values and the density of the 0.65eV and 1eV electron traps was observed. The measured lifetimes show an increase with temperature following a power law that suggests that the hole capture could be determined by cascade capture process.

High Quality 150 mm 4H SiC Wafers for Power Device Production

The commercial availability of high quality 150 mm 4H SiC wafers has aided in the growth of SiC power device fabrication. The progress of 150 mm 4H SiC wafer development at Dow Corning is reviewed. Defect densities compare well to those typical for 100 mm wafers, with even lower threading screw dislocation densities observed in 150 mm wafers. Resistivity data shows a comparable range from 0.012 – 0.025 ohm.cm, and excellent shape control is highlighted for wafer thicknesses of 350 μm and 500 μm.

Study of Polytype Switching vs. Micropipes in PVT Grown SiC Single Crystals

SiC single crystals were grown with the intention to produce 4H wafers using a physical vapor transport (PVT) technique. Polytype switching between 4H, 6H and 15R polytypes were observed and categorized into four different types. In particular, the mixed polytypes in the seed/crystal interface regions of the crystal boules were examined in detail. The corresponding changes of micropipe densities in crystal wafers associated with the polytype switching at the seed/crystal interfaces were studied using optical microscopy and KOH etching techniques. PVT growth conditions affecting polytype switching at the growth interface as well as throughout the boules in all four types of boule growths are discussed.

Prismatic Slip in PVT-Grown 4H-SiC Crystals

Basal plane slip is the most frequently observed deformation mechanism in 4H-type silicon carbon (4H-SiC) single crystals grown by the physical vapor transport (PVT) method. However, it was recently reported that dislocations in such crystals can also glide in prismatic slip systems. In this study, we observed nonuniform distributions of three sets of prismatic dislocations in a commercial 4H-SiC substrate wafer. The nonuniformity is a result of the distribution of resolved shear stress on each prismatic slip system caused by radial thermal gradients in the growing crystal boule. A radial thermal model has been developed to estimate the thermal stress across the entire area of the crystal boule during PVT growth. The model results show excellent agreement with the observations, confirming that radial thermal gradients play a key role in activating prismatic slip in 4H-SiC during bulk growth.

Homoepitaxial Chemical Vapor Deposition of up to 150 μm Thick 4H-SiC Epilayers in a 10×100 mm Batch Reactor

In this paper we present results on the growth of low-doped thick epitaxial layers on 4° off-oriented 4H-SiC using a warm-wall multi-wafer CVD system (Aixtron VP2800WW). Statistical data on doping and thickness of 25 μm to 40 μm layer growth show results similar to standard epilayer growth (5-15 μm). Improvements in thickness and doping uniformity as well as the reduction of epitaxial defects has boosted the quality of 25 μm to 40 μm thick epilayers. Laser light scattering measurements resulted in projected device yields with median values of 83% and 96% for 5×5 mm2 and 2×2 mm2 die size, respectively. This corresponds to a low epitaxial defect density of < 0.75 cm-2 in 25-40 μm thick epilayers. This paper also presents results of 60 μm to 150 μm thick epitaxial layer growth. Excellent results for doping, thickness and carrier lifetime were achieved. As an example results of a fully loaded 10×100mm run with 150 μm thick epilayers are presented. Wafer-to-wafer doping and thickness values of 3.7 % and 3.4% for sigma/mean were accomplished, respectively. Typical average lifetime values of 5 μs to 6 μs were measured on the 150 μm thick layers without post-epi treatments.

Large Area 4H SiC Products for Power Electronic Devices

Efforts to develop 150 mm 4H SiC bare wafer and epitaxial substrates for power electronic device applications have resulted in quality improvements, such that key metrics match or outperform 100 mm substrates. Total dislocation densities and threading screw dislocation densities measured for 150 mm wafers were ~4100 cm-2 and ~100 cm-2, respectively, compared with values of ~5900 cm-2 and ~300 cm-2 measured for 100 mm wafers. While median basal plane dislocation counts in 150 mm samples exceed those of the smaller platform, a nearly 45% reduction was realized, resulting in a median density of ~3900 cm-2. Epilayers grown on 150 mm substrates likewise exhibit quality metrics that are comparable to 100 mm samples, with median thickness and doping sigma/mean values of 1.1% and 4.4%, respectively.

Optimization of 150 mm 4H SiC Substrate Crystal Quality

Continuous optimization of bulk 4H SiC PVT crystal growth processes has yielded an improvement in 150 mm wafer shape, as well as a marked reduction in stacking fault density. Mean wafer bow and warp decreased by 26% and 14%, respectively, while stacking faults were nearly eliminated from wafers produced using the refined process. These quality enhancements corresponded to an adjustment to key thermal parameters predicted to control intrinsic crystal stresses, and a reduction in crystal dome curvature.

Post-Growth Micropipe Formation in 4H-SiC

Understanding the growth and propagation of defects in SiC remains of interest in an effort to continue to improve device performance. A post-growth boule heat-treatment revealed to form micropipe pairs from apparent single screw dislocations is reviewed. In the treated samples almost no 1c threading screw dislocations were found. Instead, micropipe pairs were observed in similar densities to 1c threading screw dislocations in non-heat treated samples. It is hypothesized that the elevated temperatures allowed for enhanced dislocation mobility, enabling the transition.

Studies of c-Axis Threading Screw Dislocations in Hexagonal SiC

In our study, closed-core threading screw dislocations and micropipes were studied using synchrotron x-ray topography of various geometries. The Burgers vector magnitude of TSDs can be quantitatively determined from their dimensions in back-reflection x-ray topography, based on ray-tracing simulation and this has been verified by the images of elementary TSDs. Dislocation senses of closed-core threading screw dislocations and micropipes can be revealed by grazing-incidence x-ray topography. The threading screw dislocations can be converted into Frank partial dislocations on the basal planes and this has been confirmed by transmission synchrotron x-ray topography.

Electrical Characterization of Semi-Insulating 6H-SiC Substrates

A high purity physical vapor transport (PVT) process has been developed successfully at Dow Corning Corporation to produce large area, semi-insulating 6H-SiC wafers without the addition of dopants during growth. In this study, a variety of techniques including COREMA, Hall effect measurement and two terminal I-V test, etc. were used to characterize these semi-insulating 6H-SiC wafers. Activation energy information was also obtained by temperature dependent resistivity measurement. SIMS (Secondary Ion Mass Spectroscopy) and GDMS (Gas Discharge Mass Spectroscopy) analyses were performed to identify the possible doping impurities and their concentrations in SiC crystals. Based on these data, the impact of residual dopants on the semiinsulating properties of SiC material is discussed. Introduction Silicon carbide (SiC) is a preferred substrate material for AlGaN/GaN based power microwave devices such as HEMTs [1] because of its excellent thermal conductivity and smaller lattice mismatch compared with sapphire. To minimize dielectric losses, semi-insulating SiC substrates are required. The first established technique to obtain the semi-insulating SiC wafers is to add small amounts of vanadium into the SiC crystal to compensate the residual impurities[2]. Vanadium acts as a deep acceptor or a deep donor in SiC, compensating either nitrogen or boron, respectively. However, excess metal impurities in SiC have been shown to form metal carbides and induces more defects such as micropipes, voids, and inclusions, etc. Recently, Dow Corning Corporation has developed a high purity physical vapor transport (PVT) process to produce large area (76 mm and 100mm), semi-insulating 6H-SiC substrates. The highly resistive characteristics of these SiC wafers pose a great challenge for the accurate measurement of their resistivity. In this study, we applied a variety of techniques such as Hall effect, COREMA (COntactless REsistivity MApping), and I-V test, to measure the resistivity of semiinsulating SiC substrates and compared their results. Further, residual impurities in SiC wafers and their concentrations were investigated by SIMS (Secondary Ion Mass Spectroscopy) and GDMS (Gas Discharge Mass Spectroscopy) technique. Finally, the impact of residual dopants on the semiinsulating properties of SiC material is discussed based on these data. Experiment To achieve semi-insulating SiC substrates without the addition of vanadium, it is critical to reduce the concentrations of shallow level impurities such as nitrogen and boron in SiC crystals. Nitrogen mainly comes from growth ambient, air trapped in the pores of graphite parts, residual air in the growth chamber, or source materials. Boron can originate from graphite parts and source materials. Therefore, it requires a very tight impurity control of source materials, graphite parts, and vacuum system, during the crystal growth to produce high quality semi-insulating SiC substrates. Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 669-672 doi:10.4028/www.scientific.net/MSF.457-460.669