Edwin Thaller

A low jitter triple-band digital LC PLL in 130nm CMOS

A fully integrated digital LC PLL for low jitter frequency synthesis in a standard digital 130 nm CMOS technology is presented. The PLL features a fully digital core and a digitally controlled LC oscillator. It supports triple-band operation in multi-GHz range (2.1 GHz, 3.3 GHz and 4.4 GHz) with a single programmable coil, resulting in a die area as small as 0.24 mm/sup 2/. While consuming 16 mA of current, the PLL achieves an outstanding long-term jitter of 640 fs, which compares with the most advanced analog PLLs. Its digital nature makes it easily implementable in the main stream digital CMOS technologies, robust against noise and thus ideal for application as a low jitter clock multiplying unit in digital intensive systems on chip (SoCs).

A fully integrated 13 GHz /spl Delta//spl Sigma/ fractional-n PLL in 0.13 /spl mu/m CMOS

A 13 GHz PLL designed for future WLAN systems in the 17 GHz ISM band includes a differentially tuned LC VCO, IQ-divider, 212-217 low power multi-modulus prescaler, differential phase-frequency detector, charge pump with loop filter, and a 2nd-order noise-shaping /spl Delta//spl Sigma/ modulator. Total power consumption is 60 mW from a 1.5 V supply.