Nicola Da Dalt

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1–3], offering very low jitter values in integer-N mode but not supporting fractional-N synthesis, which is desirable to implement, i.e., spread spectrum clocking (SSC) for EMI reductions. Wireless applications implement time to digital converters (TDC) [4–6] which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital PLL should be intended to eliminate.

A 0.06 mm

GSM-compliant local oscillator consuming a tiny die area of only 0.06 mm and drawing 9 mA from a 1.2 V supply has been designed in a 65 nm CMOS process using thin-oxide devices only. The system is made of a 13 to 15 GHz LC VCO followed by a divide-by-four injection-locked frequency divider. The divider employs a ring oscillator-based topology leading to a two octave locking range with limited area and power consumption. The phase noise at the output of the divider is below -133 dBc/Hz at 3 MHz offset over the tuning range.

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This paper introduces a novel architecture of digital PLL. The goal of this architecture is to reach low jitter, fractional operation, and FSK modulation capability with low architecture complexity for small area, low power, and minimal design effort. The architecture is based on the bang-bang phase detector, so that usage of time-to-digital-converter circuits is avoided, with no need for any background calibration. The key enabling blocks are a phase interpolator-based exact fractional frequency divider, and a multi-output bang-bang phase detector. The prototype implemented in 130 nm reaches 1-psrms absolute jitter while operating in integer mode and 1.9 psrms absolute jitter while operating in full fractional mode, with an output frequency of 1 GHz and reference frequency of 25 MHz, consuming 7.4 mW from a supply of 1.3 V. FSK modulation of the 1 GHz carrier up to 300 kbps with a frequency deviation of ±150 kHz is also implemented and measured .

11 mW Local Oscillator for the GSM Standard in 65 nm CMOS

In the field of digital PLLs, there is a trend to find alternatives to time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive for their low-jitter, low-power capabilities, but are limited to integer-N operation by nature. Solutions that merge the key performance of the bang-bang architecture with fractional-N operation as in [3] are needed in order to turn the bang-bang digital PLLs into real alternatives to TDC-based PLLs.

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

This paper presents the design and implementation of dual-band LC-VCOs in the GHz-range featuring a switched coil LC-tank. The proposed design exploits the self-inductance technique. The design of the coil starts from simple considerations and back-of-the-envelope calculations, then electromagnetic simulations are used to optimize the coil layout. The sizing of the switch and its impact on the VCO performance are addressed as well. The VCOs have been implemented in 65nm CMOS technology. Good correlation between simulated and measured tuning range and phase noise is obtained for all designs, thus confirming the validity and robustness of the design methodology and coil models. Copyright

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider

We present and validate against experiments a modeling approach for high-speed serial links that combines the computational advantages of statistical techniques for intersymbol interference (ISI) (improved by employing the realistic pulse shape as from SPICE simulations) and a simple empirical methodology to account for the jitter of the transmitter. The proposed approach is validated by comparison with other modeling approaches such as full SPICE simulations (for ISI) and Simulink (for jitter) as well as against the experimental data for a 2.5 Gb/s CMOS differential transmitter driving different channels.

Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique

The demand for ultra-high speed transceivers continues to rise exponentially due to the insatiable demand for high-throughput interconnect. Standards between 25 and 32Gb/s are rapidly approaching maturity, and available products and IPs at these rates are iterating to push down power while extending channel-loss recovery limits. Predictably, specifications are now in early stages for extending per-lane bandwith to between 40 and 64Gb/s. Meeting these 25Gb/s+ targets, especially for long-reach applications, is stressing the capabilities of both the underlying circuitry and the communication channels, and has caused significant rethinking of the overall system and circuit architectures for these links. In particular, the debate about multi-level (PAM4) versus binary (PAM2) signaling and which path offers the best energy-efficiency/data-rate scalability has returned to the foreground. Similarly, the emergence of high-speed ADCs with sufficient resolution for link applications has driven renewed interest in DSP-based approaches, while other efforts have pushed more analog/mixed-signal link components to over 60Gb/s/lane. To further ensure low BER operations, sophisticated coding such as FEC is brought into the discussion. Even in the domain of optical communications, significant challenges related to the bandwidth capabilities of the optical devices as well as the back end processing are currently being addressed. In fact, some of the highest speed optical links are limited by the short electrical interconnect between the driver circuitry and the optical module itself. This forum presents state-of-the-art I/O techniques enabling such high line rates across both optical and electrical interfaces as well as a number of emerging standards such as 802.3bj, various flavors of CEI, and HMC (hybrid memory cube).

Efficient Statistical Simulation of Intersymbol Interference and Jitter in High-Speed Serial Interfaces

Communications inside vehicles is experiencing a growing demand due to emerging applications, like infotainment, driver assistance, safety systems and diagnostics, requiring data-rates per channel beyond what is offered by current solutions. The number of network nodes per car has steeply increased, and the number of communication ports per year shipped for the automotive market has reached the 650-million level (Sources: IMS, SA, Gartner). Considering that cabling is the third highest cost factor and the third heaviest component in the car (Source: IEEE), there is a clear need to go beyond the current low data-rate solutions and converge to a high data-rate backbone network. Several solutions, both electrical and optical, are being discussed and proposed by car makers and silicon manufacturers. What are the future solutions going to look like, and what challenges will they pose to the solid-state circuits community?

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data

Direct injection locking applied to a ring oscillator results in a divide-by-7 frequency divider circuit with a 22% locking range, from 4.1 to 5.1 GHz. The 38 } 31 μm2 65 nm CMOS prototype draws 430 μΑ from a 1.2 V supply. The output phase noise tracks the references one with the expected 17 dB difference at small offsets, settling to a −133dBc/Hz floor at larger offsets. The integrated rms jitter of 1.9 ps is adequate for the target digital clocking applications.

ES3: High-speed communications on 4 wheels: What's in your next car?

System power consumption will drive the architecture of future computing systems. From cloud-connected smart phones to the first exaFLOP supercomputers, systems that are the best at managing and minimizing power consumption will hold a key competitive advantage. At the same time, wireline communication bandwidth requirements within these systems will continue to grow exponentially, driving per-lane data rates beyond 25Gb/s and aggregate bandwidth past 1Tb/s while demanding dramatically improved energy efficiency. The objective of this Forum is to provide an overview of ultra-efficient parallel and serial interfaces, advanced memory applications, dense and high-speed optical communication, and platform-driven wired I/O for mobile. The Forum begins with two talks describing how innovative packaging and form factors along with co-design of I/O circuits and interconnects can improve the power/performance tradeoff by more than an order of magnitude. The next two talks address how memory I/O is adapting to meet the aggressive bandwidth and power requirements for systems ranging from cell phones to supercomputers. The next talk explores how to design serial I/O specifically for mobile products, including low-power equalization and clocking and low-latency standby states. The following talk also focuses on energy-efficient clocking and equalization, but explores analog and digital design options for very high-speed link standards. The final two talks highlight recent advances in both discrete and integrated optical transceivers and the power, performance, density and cost benefits for optical in high-performance computing systems.