Peter Gregorius
Qimonda
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Publication
Featured researches published by Peter Gregorius.
international solid-state circuits conference | 2009
Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; Michael Richter; Ian Russell; Kai Schiller; Ronny Schneider; Kartik Swaminathan; Bradley Weber; Julien Weber; Ingo Bormann; Fabien Funfrock; Mario Gjukic; Wolfgang Spirkl; Holger Steffens; Jorg Weller; Thomas Hein
Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.
international solid-state circuits conference | 2007
Zheng Gu; Peter Gregorius; Daniel Kehrer; Lydia Neumann; Evelyn Neuscheler; Thomas Rickes; Hermann Ruckerbauer; Martin Streibl; Juergen Zielbauer
A memory interface operating up to 5.3Gb/s in a 70nm standard DRAM process is presented. The interface uses differential point-to-point signaling in a chain of 6 devices, in transparent- or resample-repeat mode. Transparent-repeat mode measurements at 4.8Gb/s show eye reduction of 8% Ul per device due to jitter accumulation. The last device in the repeat chain has an eye opening of 0.5UI at BER < 1012. The transparent-repeat mode consumes 40% less power and has 80% less latency than resample mode
Archive | 2007
Christoph Bilger; Peter Gregorius; Michael Bruennert; Maurizio Skerlj; Wolfgang Walthes; Johannes Stecker; Hermann Ruckerbauer; Dirk Scheideler; Roland Barth
Archive | 2005
Hermann Ruckerbauer; Simon Muff; Christian Weiss; Peter Gregorius
Archive | 2005
Hermann Ruckerbauer; Peter Gregorius
Archive | 2008
Michael Bruennert; Peter Gregorius; Georg Braun; Andreas Gaertner; Hermann Ruckerbauer; George William Alexander; Johannes Stecker
Archive | 2005
Paul Wallner; Andre Schaefer; Thomas Hein; Peter Gregorius
Archive | 2008
Andreas Schneider; Markus Balb; Thomas Hein; Christoph Bilger; Martin Brox; Peter Gregorius; Michael Richter
Archive | 2008
Peter Gregorius; Thomas Hein; Martin Maier; Hermann Ruckerbauer; Thilo Schaffroth; Ralf Schedel; Wolfgang Spirkl; Johannes Stecker
Archive | 2008
Michael Bruennert; Peter Gregorius; Georg Braun; Andreas Gaertner; Hermann Ruckerbauer; George William Alexander; Johannes Stecker