Eero Pajarre

PAR-APLAC: Parallel Circuit Analysis and Optimization

The authors describe a circuit simulation, analysis and optimization software which can utilize the most common parallel processing hardware, i.e. the workstation network. The parallel processing ability has been implemented using an easy-to-use but powerful methodology. The efficiency of this methodology is demonstrated in terms of both CPU and programmer time. The feasibility of converting even large existing software systems for at least partial parallel execution is demonstrated. With a suitable set of tools the amount of changes which are needed is small. Despite the limited bandwidth of an Ethernet network, a set of networked computers can be used as an efficient parallel processor for some of the problems in electronic design automation.<<ETX>>

Methods and algorithms for converting IC designs between incompatible design systems

Methods and algorithms are described for converting designs from a geometrical database design system to a design system which is based on basic electrical objects. The feasibility of these algorithms is demonstrated using GDS II and L language as examples. The performance of the system is such that it can be used in design verification by converting mask layouts to a format suitable for simulation.<<ETX>>

G2L: system for converting low-level geometrical designs to a higher level representation

The author presents a methodology for converting VLSI design information from a geometry oriented database to a higher level database where electrical objects are the primitive elements. The conversion extracts the active elements and implicit connections from the geometry and recreates them using novel routing techniques producing geometrically identical layout. The methodology has been implemented in a GDS II to L language converter capable of converting databases containing whole chip designs. The system has been tested with processor designs and whole standard cell libraries.<<ETX>>