Ville Eerola
Tampere University of Technology
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Featured researches published by Ville Eerola.
international symposium on circuits and systems | 1992
Ville Eerola; Harri Lampinen; Tapani Ritoniemi; Hannu Tenhunen
A method for quadrature demodulation by subsampling with sigma-delta analog-to-digital converters is discussed, and a correlator receiver structure based on this method is described. The almost completely digital demodulator structure is based on second-order sampling and sigma-delta analog-to-digital converters. A theoretical performance analysis is presented, and a measurement system for the method is described. The proposed structure can be implemented on a single integrated circuit.<<ETX>>
international symposium on circuits and systems | 1991
Ville Eerola; Tapani Ritoniemi; Hannu Tenhunen
Basic structures for transmitting and receiving any quadrature modulated signal have been developed. As an example, the structures were applied to MSK modulation, and this resulted in working MSK modulator and demodulator structures that were verified by simulations at the functional level. A very simple and compact digital VLSI implementation of a MSK modulator can be built using the structure. The only analog part is the bandpass filter, which is also required in the conventional modulator structure. The use of sigma-delta A/D-convertors makes the demodulator structure very robust. The highest clock frequency (four times the carrier frequency f/sub c/) is needed only for synchronizing purposes, and the parts would be clocked at f/sub c/.<<ETX>>
international conference on acoustics, speech, and signal processing | 1994
Jari Nurmi; Ville Eerola; Erwin Ofner; Andreas Gierlinger; Jürgen Jernej; Teppo Karema; Tommi Raita-aho
An application specific processor core for mobile speech coding applications has been designed and implemented. Since the architecture is tailored to the application, it has a very low power consumption, making it attractive for handheld devices. The low power consumption, flexible design and high performance have been achieved by a standby mode, optimized full custom design, and a low clock frequency, together with a highly parallel architecture. All the parallelism is accessible to the user on the assembler level. Engineering samples of the processor have been fabricated and tested. The silicon area required for the core is approximately 25 mm/sup 2/ using 1.0 /spl mu/m CMOS. A typical average power consumption for a GSM full rate speech codec implementation using this core is less than 50 mW at 5 V operating voltage, and the complex algorithm is executed in less than 5 ms for each 20 ms speech frame (including encode, decode, VAD and DTX operations).<<ETX>>
Ecological Economics | 1990
Tapani Ritoniemi; Ville Eerola; Teppo Karema; Hannu Tenhunen
The basic principles of oversampled noise-shaping analog-digital (A/D) and digital-analog (D/A) converters are presented. Basic operation and theory behind sigma-delta modulation are reviewed. The different structures of the sigma-delta converters are described, and the concepts of designing modulators and digital filters are discussed. The latest designs are reviewed.<<ETX>>
norchip | 2013
Ville Eerola; Jari Nurmi
This paper shows how the correlator block for GNSS receivers can be analyzed and optimized. The received signal characteristics are reviewed and used in the optimization process. The correlator is a key element in the GNSS receivers and it takes a considerable amount of the chip area and power. It is shown that a gate-count reduction of 30% or more can be achieved while also reducing the power consumption by more than 50%. The authors also discuss how advanced functionality can be added with just a minor increase of the correlator gate-count. The additional logic allows real-time configuration of the correlator hardware, which increases its usability in advanced GNSS receivers.
international conference on localization and gnss | 2014
Ville Eerola; Jari Nurmi
This paper presents the silicon area estimation of three different GNSS receiver architectures with the analysis of four different use cases. The receivers are based on traditional correlator, matched filter, and group correlator architectures. While introducing the selected test cases, the authors discuss their applicability for real-life receiver operations. The receiver architectures are described shortly and the implementation details explained. The comparison shows that the correlator based receiver suits best for tracking while matched filters are efficient only for pure search mode. The group correlator offers a good area-efficiency in both tracking and search modes.
Archive | 2000
Ville Eerola; Tapani Ritoniemi
Archive | 1994
Eero Pajarre; Ville Eerola; Tapio Saramäki; Tapani Ritoniemi; Timo Husu; Seppo Ingalsuo
Archive | 1996
Ville Eerola; Tapani Ritoniemi; Timo Husu; Marko Kyrölä; Kim Kaisti; Timo Saarnimo; Vesa Karttunen; Jukka Petteri Mäkelä
Archive | 2000
Ville Eerola; Tapani Ritoniemi