Effendi Leobandung

Observation of quantum effects and Coulomb blockade in silicon quantum‐dot transistors at temperatures over 100 K

We report the fabrication and characterization of lithographically defined nanoscale silicon quantum‐dot transistors that operate at temperatures over 100 K and a bias higher than 0.07 V. In the tunneling regime, these transistors show strong current oscillations due to quantum confinement and single‐electron charging effects. In the propagating regime, a different kind of current modulation has been observed, which is attributed to the interference between different modes of quantum waves in a cavity. Proper scaling of these transistors should lead to operation at room temperature and a bias of 0.3 V.

A ROOM-TEMPERATURE SILICON SINGLE-ELECTRON METAL-OXIDE-SEMICONDUCTOR MEMORY WITH NANOSCALE FLOATING-GATE AND ULTRANARROW CHANNEL

We have demonstrated a room-temperature silicon single-electron transistor memory that consists of (i) a narrow channel metal-oxide–semiconductor field-effect transistor with a width (∼10 nm) smaller than the Debye screening length of single electron; and (ii) a nanoscale polysilicon dot (∼7×7 nm) as the floating gate embedded between the channel and the control gate. We have observed that storing one electron on the floating gate can significantly screen the channel from the potential on the control gate, leading to a discrete shift in the threshold voltage, a staircase relationship between the charging voltage and the threshold shift, and a self-limiting charging process.

Single hole quantum dot transistors in silicon

Novel p‐channel quantum‐dot transistors were fabricated in silicon‐on‐insulator. Strong oscillations in the drain current as a function of the gate voltage have been observed at temperatures over 81 K and drain biases over 66 mV. The oscillations are attributed to holes tunneling through the discrete single hole energy levels in the quantum dot. Measurements show that the average energy level spacing is ∼35 meV. Simple modeling indicates that about two thirds of the energy level spacing come from the Coulomb interaction between holes (i.e., hole Coulomb blockade) and one third from the quantum confinement effect. The realization of single hole quantum‐dot transistors opens new possibilities for innovative circuits that utilize complementary pairs of quantum‐dot transistors.

Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects

Metal–oxide–semiconductor field-effect transistors (MOSFETs) with a wire-channel and wrap-around-gate (WW) structure were fabricated using electron beam lithography and reactive ion etching. The smallest devices have a 35 nm channel width, a 50 nm channel thickness, and a 70 nm channel length. Measurements showed that as the channel width of WW MOSFETs decreased from 75 to 35 nm short channel effects were significantly reduced: the subthreshold slope decreased from 356 to 80 mV/dec and the drain-induced barrier lowering decreased from 988 to 129 mV. Furthermore, the reduction of channel width increases the drive current per unit channel width. A multichannel WW MOSFET with a high current driving capability is discussed.

Fabrication and characterization of room temperature silicon single electron memory

A single electron memory was demonstrated in crystalline silicon that has a transistor channel width of ∼10 nm and a nanoscale floating gate of dimension ∼(7 nm × 7 nm × 2 nm), patterned by electron beam lithography, lift-off, and reactive ion etching. Quantized shift in the threshold voltage and self-limited charging process have been observed at room temperature. Analysis has shown that these quantized characteristics are the results of single electron charging effect in the nanoscale floating gate.

Single electron and hole quantum dot transistors operating above 110 K

Both single electron and hole quantum dot transistors in silicon‐on‐insulator were fabricated and characterized. The quantum dots were formed using electron‐beam nanolithography and reactive ion etching. The single electron quantum dot transistors show the oscillation of the drain current as a function of the gate voltage at temperatures up to 170 K and drain biases up to 80 mV. The oscillation is due to electron tunneling through the discrete energy levels inside the quantum dot. The average energy level spacing is ∼60 meV. Data analysis shows that the discrete energy levels are caused by Coulomb interaction as well as quantum size effects. The single hole quantum dot transistors show similar oscillations up to 110 K and drain biases up to 50 mV. The average energy level spacing is ∼36 meV.

Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length

We report the fabrication and characterization of SOI NMOSFETs with channel width as narrow as 35 nm. For the first time, it is observed that using a narrow channel width, the short channel effects in SOI MOSFETs can be significantly reduced because the gate wrapped around the narrow channel side wall allowing a better gate control in horizontal and vertical direction. With a 35 nm channel width, we are able to realize well-behaved SOI NMOSFETs with effective channel length of 70 nm.

Silicon quantum-dot transistors operating above 100 K

Reports the fabrication and characterization of unique silicon quantum-dot transistors (QDTs) that demonstrate quantum as well as single-electron Coulomb blockade effects at temperatures above 100 K. They are also the first Si transistors that show interference between different modes of quantum waves in a cavity. The transistors were fabricated on SIMOX (separation by implanted oxygen) silicon wafer with the top silicon layer 70 nm thick.