Yun Wang

Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing

We optimized the halo profile and deep source/drain junction profile of the devices that were fabricated by non-melt laser spike annealing (LSA). The optimized devices achieved 10%- and 20%-better performance compared to those by the conventional LSA and rapid thermal annealing (RTA), respectively. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. From these results we concluded that the dopant profile engineering specific to LSA is a key to obtaining good device performance and that the devices by the optimized LSA process are the most promising for hp65-node and beyond.

Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS

We have developed a novel LTP (laser thermal process) that dramatically enhances the laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). The Vth roll-offs of MOSFETs formed by this method were remarkably improved compared to those by RTA when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.

Drive Current Enhancement in Sub- 40-nm CMOS Devices by Higher Carrier Activation with Laser Spike Annealing

We thoroughly investigated the impact of higher carrier activation using laser spike annealing (LSA). In our experiments, the annealing time was set at 200 μs and the peak annealing temperature was estimated at 1350°C, which was 350°C higher than that of the spike-rapid thermal annealing (RTA) used in this study. We analyzed the source-drain parasitic resistance and the gate depletion suppression to demonstrate that LSA can improve I on currents while suppressing the short channel effect in sub-40-nm complementary metal oxide semiconductor devices, compared to the conventional spike-RTA. The gate depletion was suppressed by 0.18 and 0.15 nm for p-MOS and n-MOS devices, respectively, and, channel conductance can actually be improved with it. Using LSA, a shallower junction depth and shorter source-drain extension (SDE) overlap length was achieved for the same SDE sheet resistance. As a result, the V th roll-off improved dramatically. Moreover, the higher carrier activation produced improvements in the /on current of 3%/14% for p-MOS/n-MOS transistors. We also demonstrate that a 13% improvement in I on was achieved for p-MOS at the same V th -roll-off as the spike-RTA device, due to the simultaneous suppression of gate depletion and the reduction in the source-drain parasitic resistance.

Drive Current Enhancement in Sub-50 nm CMOS by Reduction of SDE Resistance with Laser Thermal Process

In this paper, we report on the ultrashallow junction profiles and good characteristics of sub-50 nm bulk complementary metal oxide semiconductor (CMOS) devices with n+/p+ source-drain extensions (SDEs) formed by laser thermal processing (LTP). By combining LTP with preamorphization and strong-dosage dopant-ion implantation, CMOS drive current can be improved without incurring a cost in terms of short-channel deterioration. The SDE-junction depth, SDE overlap length, and sheet resistance were controlled by the energy of preamorphization implantation, and the first two of these parameters were independent of dopant dosage. This allowed us to design strongly activated and abrupt box-like dopant profiles. With this technique, we obtain improvements in drive current of 13 and 8%, respectively, for p- and n-metal oxide semiconductor field effect transistors at V d = ∓1 V and I off = 100 nA/μm without inducing any short-channel deterioration.

Drive current enhancement by ideal junction profile using laser thermal process

In this paper, for the first time, we report the characteristics of sub-50 nm pMOSFETs using a laser thermal process (LTP) and the technique for enhancing their drive current. For the process optimization required for the technologies of sub-50 nm MOSFETs, we investigated the issues of LTP and cleared them up. S/D-extension (SDE)-junction depth, overlap and sheet resistance were controlled by pre-amorphization ion implantation (I/I) energies, and the first two parameters could be thus controlled regardless of dopant dose. This enabled us to design highly activated and abrupt box-like dopant profiles without inducing any short channel deterioration. With this technique, we achieved higher drive current pMOSFETs for the same V/sub th/-rolloff and a 13% improvement in drivability for 45 nm pMOSFETs.

Laser thermal annealed SSR well prior to epi-channel growth (LASPE) for 70 nm nFETS

Laser thermal annealed super-steep retrograded well prior to epi-channel growth (LASPE) was designed to prevent a severe B loss causing an anomalous V/sub t/ lowering for SSR nFETs, which usually occurred during epi-channel (EC) growth, and to freeze SSR doping profile upon subsequent annealing. Shallow (<50 A) melting by laser thermal annealing (LTA) leads to a backward shift of /spl delta/-type B peak along with increasing peak broadness while suppressing B loss remarkably upon EC growth and RTA. The amount of /spl delta/-peak shift increases with EC thickness, and is found to freeze without further TED upon RTA. Compared to conventional epi-channel devices, improved short channel and junction leakage characteristics with reasonable V, but slightly degraded long-channel S-factor were obtained by employing 70 nm LASPE nFETs. The body effect was also found to be independent of channel width variation, implying no B TED and segregation into the isolation oxide edges.

Suppression of gate depletion in p+-polysilicon-gated sub-40 nm pMOSFETs by laser thermal processing

Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40 nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at Ioff=70 [nA/µm] that is 4% greater than that in a device fabricated using conventional RTA. The off-state Ig current that flows mainly from the p+ poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.

Realization of Low CoSi2/p+-Silicon Contact Resistance with Low Junction Leakage Current and Junction Capacitance Using Laser Thermal Process

In this paper we report source–drain engineering for the realization of low contact resistance between CoSi2 and p+ Si with low junction leakage current and low junction capacitance using laser thermal processing (LTP) and the optimization of ion implantation conditions. We first demonstrate the impact of pre-amorphization on the reduction of the contact resistivity of a CoSi2/p+ deep source–drain (deep-SD) interface using laser thermal processing (LTP). A highly activated dopant profile at the CoSi2/deep-SD interface is required to reduce the contact resistivity there. Dopant profile can be finely controlled by implanting heavy ions to preamorphize a region to the desired depth and then using an appropriate laser power to selectively melt the amorphous Si, which has a melting temperature lower than that of single-crystal Si. We can thus form a highly activated boxlike dopant profile suitable for a deep-SD by using LTP and relatively deep preamorphization. Then, we discuss how to suppress the leakage current and the capacitance of the junctions. The larger junction capacitance and junction leakage current due to the abrupt deep-SD profile can be greatly reduced by combining LTP with lower-dose, higher-energy implantation and RTA prior to preamorphization (predoping and pre-RTA) to form a graded deep-SD profile beyond the abrupt deep-SD profile and overwhelm the channel doping profile, resulting in a wide depletion layer.

Suppression of Gate Depletion in p+ Polysilicon Gated Sub-40nm PMOS Devices by Laser Thermal Process

Introduction For aggressively scaling of CMOS devices, thinner gate oxide is required, and at the same time, suppression of gate depletion is also important. Low thermal budget source-drain rapid thermal annealing (SD-RTA) processing becomes more important to maintain shallow junctions for well-controlled short channel effects. However, low thermal budget SD-RTA tends to induce severe poly-Si gate depletion due to low dopant diffusivity and activation and, as a result, device performance is degraded. Thus, gate pre-doping and pre-annealing technique becomes more important to control thermal budget for SD annealing independently [1,2]. Fig. 1 shows the electrical inversion oxide thickness and threshold voltage (Vth) shift as a function of gate annealing conditions for p+ poly-Si gated PMOSFET as an example. By applying gate pre-annealing, gate depletion is clearly suppressed and higher annealing temperature is more effective due to higher dopant diffusion and activation. However, at the same time, high temperature annealing tend to induce the positive shift of Vth due to boron penetration through the gate oxide and into the channel region. In our experiments, 0.01nm improvement requires 80mV of Vth shift (see low to high temperature). This implies that suppression of gate depletion and boron penetration, which causes performance degradation, Vth variation and reliability issues tend to fall into the relations of the trade-off. Recently, gate activation by laser thermal process (LTP) has been reported [3], and its characteristics of sub-40nm MOSFETs have also been reported [4,5]. In this paper, we report, for the first time, that LTP as a gate pre-annealing is superior to RTA for both gate activation and suppression of boron penetration.