Lingjie Guo

Sub-10 nm imprint lithography and applications

Nanoimprint lithography (NIL) is a new lithography paradigm that is based on deformation of a resist by compression molding rather than altering its chemical structure by radiation, and is designed to fabricate nanostructures inexpensively with high throughput. In this paper, we present significant new developments in achieving holes and dots with 6 nm feature size, 40 nm period on silicon, and 10 nm feature size, 40 nm period on a Au substrate. Moreover, we present an application of NIL to the fabrication of nanoscale compact disks (NanoCDs) of 400 Gbits/in/sup 2/ data density.

Silicon single-electron quantum-dot transistor switch operating at room temperature

We fabricated a silicon single-electron quantum-dot transistor, which showed drain current oscillations at room temperature. These oscillations are attributed to electron tunneling through a single silicon quantum dot inside a narrow wire channel. Analysis of its current–voltage characteristic indicates that the energy level separation is about 110 meV and the silicon dot diameter is about 12 nm.

Observation of quantum effects and Coulomb blockade in silicon quantum‐dot transistors at temperatures over 100 K

We report the fabrication and characterization of lithographically defined nanoscale silicon quantum‐dot transistors that operate at temperatures over 100 K and a bias higher than 0.07 V. In the tunneling regime, these transistors show strong current oscillations due to quantum confinement and single‐electron charging effects. In the propagating regime, a different kind of current modulation has been observed, which is attributed to the interference between different modes of quantum waves in a cavity. Proper scaling of these transistors should lead to operation at room temperature and a bias of 0.3 V.

Nanoscale silicon field effect transistors fabricated using imprint lithography

We report the fabrication and characterization of nanoscale silicon field effect transistors using nanoimprint lithography. With this lithographic technique and dry etching, we have patterned a variety of nanoscale transistor features in silicon, including 100 nm wire channels, 250-nm-diam quantum dots, and ring structures with 100 nm ring width, over a 2×2 cm lithography field with good uniformity. Compared with devices fabricated by the conventional electron-beam lithography, we did not observe any degradation in the device characteristics. The successful fabrication of the semiconductor nanodevices represents a step forward to make nanoimprint lithography a viable technique for the mass production of semiconductor devices.

A ROOM-TEMPERATURE SILICON SINGLE-ELECTRON METAL-OXIDE-SEMICONDUCTOR MEMORY WITH NANOSCALE FLOATING-GATE AND ULTRANARROW CHANNEL

We have demonstrated a room-temperature silicon single-electron transistor memory that consists of (i) a narrow channel metal-oxide–semiconductor field-effect transistor with a width (∼10 nm) smaller than the Debye screening length of single electron; and (ii) a nanoscale polysilicon dot (∼7×7 nm) as the floating gate embedded between the channel and the control gate. We have observed that storing one electron on the floating gate can significantly screen the channel from the potential on the control gate, leading to a discrete shift in the threshold voltage, a staircase relationship between the charging voltage and the threshold shift, and a self-limiting charging process.

Single hole quantum dot transistors in silicon

Novel p‐channel quantum‐dot transistors were fabricated in silicon‐on‐insulator. Strong oscillations in the drain current as a function of the gate voltage have been observed at temperatures over 81 K and drain biases over 66 mV. The oscillations are attributed to holes tunneling through the discrete single hole energy levels in the quantum dot. Measurements show that the average energy level spacing is ∼35 meV. Simple modeling indicates that about two thirds of the energy level spacing come from the Coulomb interaction between holes (i.e., hole Coulomb blockade) and one third from the quantum confinement effect. The realization of single hole quantum‐dot transistors opens new possibilities for innovative circuits that utilize complementary pairs of quantum‐dot transistors.

Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects

Metal–oxide–semiconductor field-effect transistors (MOSFETs) with a wire-channel and wrap-around-gate (WW) structure were fabricated using electron beam lithography and reactive ion etching. The smallest devices have a 35 nm channel width, a 50 nm channel thickness, and a 70 nm channel length. Measurements showed that as the channel width of WW MOSFETs decreased from 75 to 35 nm short channel effects were significantly reduced: the subthreshold slope decreased from 356 to 80 mV/dec and the drain-induced barrier lowering decreased from 988 to 129 mV. Furthermore, the reduction of channel width increases the drive current per unit channel width. A multichannel WW MOSFET with a high current driving capability is discussed.

Fabrication and characterization of room temperature silicon single electron memory

A single electron memory was demonstrated in crystalline silicon that has a transistor channel width of ∼10 nm and a nanoscale floating gate of dimension ∼(7 nm × 7 nm × 2 nm), patterned by electron beam lithography, lift-off, and reactive ion etching. Quantized shift in the threshold voltage and self-limited charging process have been observed at room temperature. Analysis has shown that these quantized characteristics are the results of single electron charging effect in the nanoscale floating gate.

Charge-ring model for the charge-induced confinement enhancement in stacked quantum-dot transistors

A model is proposed to explain the charge-induced confinement enhancement observed in a stacked quantum-dot transistor that has a floating dot on top of a channel quantum dot. The model assumes that the charge on the floating dot distributes on its rim, forming a ring and creating a confinement potential that squeezes the electrons in the channel dot toward its center. The charge on the floating dot can be calculated from the device geometry and from the measured threshold voltage difference before and after the charging. Given the charge on the floating dot, the spatial confinement and the energy level spacing increase induced by the charging can be obtained. The calculation based on the model agrees with the observed increase of the energy level spacing.

Single electron and hole quantum dot transistors operating above 110 K

Both single electron and hole quantum dot transistors in silicon‐on‐insulator were fabricated and characterized. The quantum dots were formed using electron‐beam nanolithography and reactive ion etching. The single electron quantum dot transistors show the oscillation of the drain current as a function of the gate voltage at temperatures up to 170 K and drain biases up to 80 mV. The oscillation is due to electron tunneling through the discrete energy levels inside the quantum dot. The average energy level spacing is ∼60 meV. Data analysis shows that the discrete energy levels are caused by Coulomb interaction as well as quantum size effects. The single hole quantum dot transistors show similar oscillations up to 110 K and drain biases up to 50 mV. The average energy level spacing is ∼36 meV.