Effiong Ibok

A Characterization of the Effect of Deposition Temperature on Polysilicon Properties Morphology, Dopability, Etchability, and Polycide Properties

Low pressure chemically vapor deposited polysilicon deposition was studied from 525 to 650 C. The silicon appears to be amorphous with a smooth surface up to 550 C and completely crystalline above 600 C. The transition region is found to be from 560 to 590 C. This transition is marked by sharp crystallographic and resistivity changes. The smooth surface morphology of the amorphous silicon is found to be preserved after POCl[sub 3] doping and a 1,000 C oxidation. The preservation of this smooth morphology is demonstrated to be due to the presence of a native oxide on the surface of the silicon upon exposure to atmosphere. However, an in situ anneal of amorphous silicon at 610 C results in large coarse crystals with rough surface morphology and disparate orientation. The smooth morphology of the 550 C silicon is found to be transmitted through subsequent polycide structure layers. The impact on device reliability is discussed. The amorphous silicon is found to have a higher plasma etch rate than the polysilicon.

Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-/spl Aring/ gate oxide MOSFETs

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.

Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).

A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROMs. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme. With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved.<<ETX>>

Determining effective dielectric thicknesses of metal‐oxide‐semiconductor structures in accumulation mode

Metal‐oxide‐semiconductor (MOS) capacitance–voltage (C–V) characteristics in the accumulation mode have been measured and simulated for polycrystalline Si gate MOS capacitors with various oxide thicknesses (40–200 A) on p‐type (100) Si substrates. The discrepancy between experimental data and theoretical prediction by classical MOS theories is clarified by taking quantization effects into account. The experimentally determined ‘‘effective dielectric thicknesses’’ in the semiconductors are found to be in good agreement with the values calculated from quantization effects for MOS capacitors with thinner oxides (<80 A). The effective dielectric thicknesses at oxide electric fields of 2–6 MV/cm have been determined to be 2–3 A larger for the quantum mechanical case than for the classical case.

Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics

Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to thermal oxide in the 2.5-nm regime. The oxynitride showed an enhanced high field effective mobility relative to the thermal oxide although the low field mobility was slightly depressed. The N/sub 2/O nitrided oxide showed an enhanced high field effective mobility with no degradation in low field mobility. The interface state density of the oxynitride was equivalent to that of the thermal and nitrided thermal oxides; a very welcome observation for this deposition chemistry and anneal conditions.

Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides

Summary form only given. In this paper, we report the performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling (DT) gate oxides. Both pure oxides and nitrided oxides down to 17 /spl Aring/ were investigated. For a L/sub g/ of about 90 nm (L/sub eff/ of about 50 nm), a drive current of larger than 1.0 mA//spl mu/m and a transconductance of higher than 800 mS/mm were obtained at room temperature. Channel electron transport properties were investigated. High field mobility degradation with decrease of oxide thickness and subsequent improvement with use of nitrided oxides were observed. Reliability characteristics such as gate leakage, stress-induced-leakage, and hot-carrier degradation are described. A new mechanical stress induced leakage phenomenon for ultra thin DT oxides was revealed.

Optical characterization of amorphous and polycrystalline silicon films

This paper describes a methodology that has been incorporated into a fully integrated measurement system, the n&k Analyzer, that determines simultaneously the thickness, energy band gap, and n and k spectra (from 190 to 900 nm) of various forms of silicon, i.e., a-Si, poly-Si films, and mixtures of a-Si and poly-Si films. Additionally, the system also measures the average surface roughness. In turn, the n and k spectra of such films can be correlated to processing conditions, temperature being the most important one in LPCVD method. The n&k Analyzer can be used to identify the amorphous-polycrystalline transition regime and characterization of films produced in this regime.

A characterization of PECVD TEOS BPSG planarity and metal-field Vt on a submicron CMOS EPROM

The planarity and metal-field Vt of PECVD TEOS BPSG were studied on an 0.8 micron technology CMOS EPROM structure. Film planarity was found to depend, primarily on boron concentration for any given thickness. A correlation between boron concentration, flow angle over an isolated poly lead and planarity in the array is established. Array planarity was found to improve with thickness. However, no noticeable difference in planarity was observed between a 7.5 kA film and a 9 kA film. Perfect array planarity is demonstrated. A correlation between film thickness and contact aspect ratio is also presented. A correlation between film oxide charge as measured by surface charge analysis and metal-field Vt is established. The n-channel field Vt decreased with increase in oxide charge, which indicates the charge is positive. The charge is concluded to be restricted to the BPSG layer.<<ETX>>