Khaled Ahmed

On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?

Negative bias temperature instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift (DeltaVT) and its field (EOX), temperature (T) and time (t) dependencies obtained from no-delay on-the-fly linear drain current (IDLIN) measurements are carefully compared to that obtained from charge pumping (CP). It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps (DeltaNIT). Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping (DeltaNh) in pre-existing bulk traps. A physics based model is developed to explain the experimental results.

On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications

Negative bias temperature instability (NBTI) is studied in p-MOSFETs having decoupled plasma nitrided (DPN) gate oxides (EOT range of 12 Aring through 22Aring). Threshold voltage shift (DeltaVT) is shown to be primarily due to interface trap generation (DeltaNIT) and significant hole trapping (DeltaNOT) has not been observed. DeltaVT follows power-law time (t) dependence and Arrhenius temperature (T) activation

Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-/spl Aring/ gate oxide MOSFETs

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.

Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) I DLIN Technique

An ultra-fast on-the-fly (UF-OTF) IDLIN technique having 1 mus resolution is developed and used to study gate insulator process dependence of NBTI in silicon oxynitride (SiON) p- MOSFETs. The nitrogen density at the Si-SiON interface and the thickness of SiON layer are shown to impact temperature, time, and field dependencies of NBTI. The plausible material dependence of NBTI physical mechanism is explored.

Gate Leakage vs. NBTI in Plasma Nitrided Oxides: Characterization, Physical Principles, and Optimization

Since nitrided oxides improve gate leakage at the expense of NBTI, one must optimize nitrogen concentration in oxinitride samples for reliable performance and reduced power dissipation. Here, we analyze wide range of NBTI stress data to develop a predictive model for gate leakage and first self-consistent model for field acceleration within R-D framework. This model anticipates a novel design diagram for co-optimization of leakage and NBTI for arbitrary nitrogen concentration and effective oxide thickness

The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly

Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly IDLIN technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface.

I_{\rm DLIN}

A comprehensive, physics-based unified model is developed for study of low resistivity metal-insulator-semiconductor (M-I-S) ohmic contact. Reduction in metal-induced gap state density and Fermi unpinning in semiconductor as a function of insulator thickness is coupled with electron transport including tunnel resistance through the metal-insulator-semiconductor (M-I-S) system to calculate specific contact resistivity at each insulator thickness for n-Si, n-Ge, and n-InGaAs. Low conduction band offset results in ∼1×10−9 Ω−cm2 contact resistivity with TiO2 insulator on n-Si, ∼7×10−9 Ω−cm2 can be achieved using TiO2 and ZnO on n-Ge, and ∼6×10−9 Ω−cm2 can be achieved with CdO insulator on n-InGaAs, which meet the sub-22nm CMOS requirements.

Technique

Flicker noise is studied in SiON p-MOSFETs before and after NBTI stress. Pre-stress noise magnitude and slope are correlated and used to verify N density distribution in gate dielectric. Post-stress noise magnitude and slope are used to explore distribution of trap generation during NBTI stress, and independently verified by using MFCP measurements. Consequence of N distribution (in SiON) on NBTI stress and recovery results is shown.

A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs

An ultrafast on-the-fly technique is developed to study linear drain current (I DLIN) degradation in plasma and thermal oxynitride p-MOSFETs during negative-bias temperature instability (NBTI) stress. The technique enhances the measurement resolution (ldquotime-zerordquo delay) down to 1 mus and helps to identify several key differences in NBTI behavior between plasma and thermal films. The impact of the time-zero delay on time, temperature, and bias dependence of NBTI is studied, and its influence on extrapolated safe-operating overdrive condition is analyzed. It is shown that plasma-nitrided films, in spite of having higher N density, are less susceptible to NBTI than their thermal counterparts.

A comprehensive study of flicker noise in plasma nitrided SiON p-MOSFETs: process dependence of pre-existing and NBTI stress generated trap distribution profiles

The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.