Shyam Garg

A Characterization of the Effect of Deposition Temperature on Polysilicon Properties Morphology, Dopability, Etchability, and Polycide Properties

Low pressure chemically vapor deposited polysilicon deposition was studied from 525 to 650 C. The silicon appears to be amorphous with a smooth surface up to 550 C and completely crystalline above 600 C. The transition region is found to be from 560 to 590 C. This transition is marked by sharp crystallographic and resistivity changes. The smooth surface morphology of the amorphous silicon is found to be preserved after POCl[sub 3] doping and a 1,000 C oxidation. The preservation of this smooth morphology is demonstrated to be due to the presence of a native oxide on the surface of the silicon upon exposure to atmosphere. However, an in situ anneal of amorphous silicon at 610 C results in large coarse crystals with rough surface morphology and disparate orientation. The smooth morphology of the 550 C silicon is found to be transmitted through subsequent polycide structure layers. The impact on device reliability is discussed. The amorphous silicon is found to have a higher plasma etch rate than the polysilicon.

A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROMs. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme. With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved.<<ETX>>

A Study of Electrical, Metallurgical, and Mechanical Behaviors of Rapid Thermal Processed Ti Films in NH 3

The electrical, metallurgical, and mechanical behavior of the Ti films heat-treated in a rapid thermal processor in NH 3 and N 2 ambient in the temperature range of 550 to 750 o C were studied. In addition, formation of the TiN film by rapid thermal nitridation (RTN) in NH 3 ambient and its barrier integrity were also studied as a function of the nitridation temperature and duration. n + and p + -type silicon and thermal oxide were used as substrates. Electron spectroscopy for chemical analysis, Rutherford backscattering spectroscopy, and sputtered neutral mass spectrometry were used to study the extent of the interactions between N, Ti, and Si as well as identification of the TiN phase and its thickness

Determining effective dielectric thicknesses of metal‐oxide‐semiconductor structures in accumulation mode

Metal‐oxide‐semiconductor (MOS) capacitance–voltage (C–V) characteristics in the accumulation mode have been measured and simulated for polycrystalline Si gate MOS capacitors with various oxide thicknesses (40–200 A) on p‐type (100) Si substrates. The discrepancy between experimental data and theoretical prediction by classical MOS theories is clarified by taking quantization effects into account. The experimentally determined ‘‘effective dielectric thicknesses’’ in the semiconductors are found to be in good agreement with the values calculated from quantization effects for MOS capacitors with thinner oxides (<80 A). The effective dielectric thicknesses at oxide electric fields of 2–6 MV/cm have been determined to be 2–3 A larger for the quantum mechanical case than for the classical case.

Manufacturing issues related to RTP induced overlay errors in a global alignment stepper technology

The effect of rapid thermal processing on wafer distortion and overlay accuracy in global alignment photolithography in the fabrication of 0.85 /spl mu/m CMOS Flash EPROM integrated circuits was studied. Both rapid thermal process parameters and system design (single and multi-lamp processors) were evaluated for their effect on overlay accuracy. It was found that a rapid thermal process (following contact etch and ion implantation) at set temperatures greater than or equal to 950/spl deg/C resulted in interconnect metallization-to-contact overlay errors in excess of 1.0 /spl mu/m across the wafer, which led to a 20% functional circuit yield loss. In the case of the single lamp processor, this misalignment was attributed to wafer distortion due to the temperature overshoot during the ramp step, which subsequently resulted in an across wafer temperature range of greater than 120/spl deg/C. This temperature overshoot and nonuniformity was eliminated by reducing the ramp rate below 100/spl deg/C/s. This ramp rate reduction, however, decreased the system wafer throughput, and required optimization to eliminate the overlay errors and minimize the effect on throughput. In this study, a 60/spl deg/C/s ramp rate was found to be optimum. For the multi-lamp RTP system, the metal-to-contact overlay error was not observed. This was believed to be due to the design of the heating mechanism in the multi-lamp processor, which did not produce the large wafer temperature overshoot and nonuniformity that was observed in the single lamp processor.

A multilevel approach toward quadrupling the density of flash memory

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake.

Conventional contact interconnect technology as an alternative to contact plug (W) technology for 0.85 /spl mu/m CMOS EPROM IC devices

The conventional (plug-less) and tungsten (W) plug contact interconnect technologies were studied for the fabrication of 0.85 /spl mu/m CMOS EPROM integrated circuit devices. 4 Mbit EPROM devices and appropriate test structures were fabricated using these two interconnect architectures and were evaluated for process simplicity, associated problems/solutions, contact electrical characteristics, and circuit yield and speed. The most important process issue for the conventional contact technology was the overlay accuracy of the stepper used for printing the contacts. It was found that a misalignment of >

Improved EEPROM tunnel- and gate-oxide quality by integration of a low-temperature pre-tunnel-oxide RCA SC-1 clean

The effects of integration of a low-temperature RCA standard clean-1 (SC1) on the tunnel- and gate-oxide charge-to-breakdown (Q/sub BD/) and voltage ramped dielectric breakdown (VRDB) distribution in a 0.7 /spl mu/m CMOS EEPROM process technology were studied. A low-temperature ( 80/spl deg/C) SC1. The reduced silicon diode etchrate of the low-temperature SC1 allowed for additional gate-oxide annealing during the gate oxidation cycle, while keeping the overall thermal budget (Dt)/sup 1/2/ for the technology equivalent to that with the higher temperature SC1. This resulted in improved gate-oxide VRDB distributions and QED values on large capacitor structures. The tunnel-oxide QBD improvement was most likely due to reduced surface roughness in the tunnel-oxide window regions with the lower temperature SC1. The process including the low-temperature SC1 was also proven to provide equivalent yield to the process with the high temperature SC1 on a 0.7 /spl mu/m, 7 nS 128 macrocell EEPROM programmable logic device.

Optical characterization of amorphous and polycrystalline silicon films

This paper describes a methodology that has been incorporated into a fully integrated measurement system, the n&k Analyzer, that determines simultaneously the thickness, energy band gap, and n and k spectra (from 190 to 900 nm) of various forms of silicon, i.e., a-Si, poly-Si films, and mixtures of a-Si and poly-Si films. Additionally, the system also measures the average surface roughness. In turn, the n and k spectra of such films can be correlated to processing conditions, temperature being the most important one in LPCVD method. The n&k Analyzer can be used to identify the amorphous-polycrystalline transition regime and characterization of films produced in this regime.

A characterization of PECVD TEOS BPSG planarity and metal-field Vt on a submicron CMOS EPROM

The planarity and metal-field Vt of PECVD TEOS BPSG were studied on an 0.8 micron technology CMOS EPROM structure. Film planarity was found to depend, primarily on boron concentration for any given thickness. A correlation between boron concentration, flow angle over an isolated poly lead and planarity in the array is established. Array planarity was found to improve with thickness. However, no noticeable difference in planarity was observed between a 7.5 kA film and a 9 kA film. Perfect array planarity is demonstrated. A correlation between film thickness and contact aspect ratio is also presented. A correlation between film oxide charge as measured by surface charge analysis and metal-field Vt is established. The n-channel field Vt decreased with increase in oxide charge, which indicates the charge is positive. The charge is concluded to be restricted to the BPSG layer.<<ETX>>