Eiji Yamamoto

A 10b 3MSample/s CMOS cyclic ADC

This low-power, small-area, 10 b 3 MSample/s (0.33 /spl mu/s) CMOS on-chip ADC uses an improved recursive subranging approach. A multi-path cyclic-conversion architecture, an implementation of a recursive subranging architecture, is proposed to further reduce the power by reducing the required circuit speed. As a result, this ADC achieves compatibility between the low-power and small-area requirements. For on-chip system application, a module that includes bus interface circuitry and buffer amplifiers for the reference-voltage generators is implemented in addition to the 10 b 3 MSample/s ADC.

Elastic shared resource scheduling SOC interconnect architecture for real-time system

We developed an elastic shared resource scheduling SoC interconnect architecture for SoCs that execute various real-time tasks in parallel. It provides both reliability for the hard real-time executions and an optimized overall performance. To meet these requirements, we introduced a hybrid-type scheduling architecture with a static scheduling block for the reliability and a dynamic scheduling block for the efficiency improvement. The dynamic scheduling block taking into consideration the progress of each task makes use of the shared resource utilizations of some tasks that have timing margins for deadlines, and optimizes the overall systems performance. We evaluated the architecture using simple model simulations and benchmarks for multimedia operations. The benchmarks show that the architecture improves the system performance by 23%. This is suitable for consumer-oriented embedded SoCs with severe restrictions on their real-time executions and system costs