Takahiro Irita

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead

A resume-standby application processor for 3G cellular phones

A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98/spl mu/A when the power supply is internally cut off.

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU

The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds of media IPs; and the interconnect buffer (ICB) extends its function to involve the IP-MMU.

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS

A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA and GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS. A CPU core standby mode with resume cache reduces leakage current of each CPU to 0.04mA when idle. A dynamic bus clock-stop scheme further reduces power consumption. Interconnect buffers allow the chip to support 30f/s VGA video.

A 342mW mobile application processor with full-HD multi-standard video codec

Todays cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally intensive than conventional standard-definition (SD) video. The trade-off between flexibility, performance and power consumption is a key focus of video-codec design. Homogeneous multi-core processors are power-consuming and achieving high-throughput is difficult [1]. While dedicated circuits can minimize power consumption, the dedicated decoders and encoders in previous reports [2, 3] have difficulty performing all of the media processing that is indispensable for a modern cellular phone [4]. In this paper, we have integrated a mobile application processor featuring a two-stage-processing video codec, tile-based address-translation circuits, and several audio/visual intellectual property (IP) modules.

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

An in situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in product-level LSIs, was developed. The design of the on-chip voltage sampling probe is based on a simple ring oscillator, which converts local supply difference between VDD and VSS to oscillation-frequency deviation. High measurement accuracy is achieved by off-chip digital signal processing and calibration. This scheme was used to successfully measure 69-mV local supply noise with 5-ns time resolution in a 3G-cellular-phone processor. It will thus help in designing power-supply networks and in visually verifying the quality of a power supply

4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−7 random hardware failures per hour reliability

The role of car information systems (commonly referred to as car infotainment) is expanding from dedicated navigation systems to joint car-cockpit systems, including the dashboard meter, telematics for the internet/cloud, and advanced driver-assistance systems (ADASs), such as adaptive cruise control and a pre-crash safety system. The expanding role for car information systems requires higher computational performance, but also safety mechanisms which prevent serious accidents. This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heterogeneous CPUs and a high level of safety, complying with ISO26262 ASIL-B. It has two key features: 1) Run-time test for functional safety, which can detect wear-out faults, such as random fault, time-dependent dielectric breakdown, and electromigration; 2) A killer-droop (critical voltage droop) monitor with droop prediction, which can avoid a delay fault caused by voltage droop.

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor

The increase in the use and number of smartphone devices is causing heavy data traffic volumes on existing 3G mobile wireless networks. LTE, often referred to as 4G, offers true mobile broadband. It is a new network and access technology that provides new spectrum resources, much increased spectral efficiency, higher throughputs (150Mb/s with higher rates to come), at lower latency and it uses an IP-based infrastructure. LTE is the solution to mitigate the traffic load issue and it is being rolled out around the world. The proposed communication processor R-Mobile U2 (RMU2) achieves single-chip integration of a 1.5GHz dual-core application processor and a triple mode (GSM/WCDMA/LTE) base-band processor. Key design highlights of the RMU2 are: 1) A 28nm HKMG high-performance and low-leakage (HPL) CMOS bulk process achieves an optimal balance between both low leakage current and high performance. 2) A CPU clock control mechanism, called the “power saver”, limits the CPU power so as not to exceed a threshold level and to reduce IR drop. 3) The internal power domain is separated into 33 sub-blocks with I/O NMOS power switches [1] to minimize leakage current of any unused sub-block. 4) A dual-mode low-leakage SRAM [2] achieves low standby current in addition to conventional memory characteristics.

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs and virtual address space can be allocated when necessary and can be freed after its operation, reducing external memory by 43 MB. Video performance of D1 (720 times 520) size with 30 frames per second for MPEG/AVC decoding and encoding can be achieved under mixed virtual and physical address usage.

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems

Todays car information systems (CIS) are growing into integrated cockpit systems, supporting not solely infotainment, such as navigation and AV playing/recording, but also driver assistance, such as surround view systems. Also, in-car video transfer via Ethernet is becoming widespread. Such networks connect camera modules, head unit controllers and rear-seat display units, and carry video signals encoded in H.264 according to EthernetAVB. Thus, it is necessary for integrated cockpit systems to handle significant amounts of video processing. A key requirement for such systems is also low power consumption and thermal management for stable operation.