Shinichi Yoshioka

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor

A power-management scheme for a single-chip multi-CPU processor uses 20 power domains. The scheme enables the minimization of leakage currents in each operating mode: 299muA in paging operation and 7muA in stand-by. The techniques for controlling and implementing power domains are also described

A resume-standby application processor for 3G cellular phones

A 389MIPS application processor for 3G cellular phones is implemented in a 0.13/spl mu/m dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98/spl mu/A when the power supply is internally cut off.

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU

The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds of media IPs; and the interconnect buffer (ICB) extends its function to involve the IP-MMU.

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS

A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA and GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS. A CPU core standby mode with resume cache reduces leakage current of each CPU to 0.04mA when idle. A dynamic bus clock-stop scheme further reduces power consumption. Interconnect buffers allow the chip to support 30f/s VGA video.

A 342mW mobile application processor with full-HD multi-standard video codec

Todays cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally intensive than conventional standard-definition (SD) video. The trade-off between flexibility, performance and power consumption is a key focus of video-codec design. Homogeneous multi-core processors are power-consuming and achieving high-throughput is difficult [1]. While dedicated circuits can minimize power consumption, the dedicated decoders and encoders in previous reports [2, 3] have difficulty performing all of the media processing that is indispensable for a modern cellular phone [4]. In this paper, we have integrated a mobile application processor featuring a two-stage-processing video codec, tile-based address-translation circuits, and several audio/visual intellectual property (IP) modules.

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones

We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointerbased pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through μI/O circuits to prevent invalid signal transmission. in the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In (he U-standby mode, (he power supply to the URAM is also turned oil for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 μA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs and virtual address space can be allocated when necessary and can be freed after its operation, reducing external memory by 43 MB. Video performance of D1 (720 times 520) size with 30 frames per second for MPEG/AVC decoding and encoding can be achieved under mixed virtual and physical address usage.

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management

A Dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the Partial Clock Activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory.

SH-MobileG1: A single-chip application and dual-mode baseband processor

This article consists of a collection of slides from the authors conference presentation on Renesas SH-MobileG1, a single chip application and dual-mode baseband processor. Some of the specific topics discussed include: presrents an overview of the company and its product line; the architecture of SH-MobileG1; 3 CPU configuration; communications architectures; interrupt control facilities; system control capabilities; and power control and leakage current measurements. Also summarizes the feature features and processing capabilities of the SH-MobileG1 line.

SH-mobile - low power application processor for cellular [3G cellular phones]

Renesas Technology Corp. gains world wide support in the field of application processors for cellular phones (SH-mobile), where various performance demanding applications must be handled with very low power consumption. Techniques of the SH-mobile to reduce leakage current, such as a partial power shut down mechanism and a methodology of multi-threshold transistors are introduced. Also advantages of the SH-mobile architecture, such as dual CPU core, large internal memory, and various media accelerators, are described from a low power consumption point of view.