Eisaku Itoh

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K*4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 mu m*7.2 mu m and a die size of 6.09 mm*12.94 mm, is fabricated by using 0.5- mu m triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle. >

A 6 ns 1 Mb CMOS SRAM with high-performance sense amplifier

A 1-Mb (256 K*4) SRAM with an access time of 6 ns using a 0.5- mu m CMOS technology is described. Fast access and low power dissipation are achieved by using a new nMOS source-controlled latched sense amplifier and a data output pre-reset circuit that reduces the output transition time.<<ETX>>