Hidenori Nomura

Dynamic random access memory having improved refresh timing

Semiconductor memory device having a CMOS sense amplifier

Dynamic random access memory

Semiconductor memory device having data bus reset circuit

Memory device employing address multiplexing

Word line multi-selection circuit for a memory device

Voltage reducing circuit

Semiconductor memory device having improved controlling function for data buses

Data amplifying system in semiconductor memory device

Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device