Teruo Seki

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K*4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 mu m*7.2 mu m and a die size of 6.09 mm*12.94 mm, is fabricated by using 0.5- mu m triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle. >

A 1-V operating 256-kb full-CMOS SRAM

A full CMOS six-transistor memory cell was fabricated with single-polysilicon, double-metal technology. The channel lengths of n-channel and p-channel transistors are 0.8 μm and 1.2 μm and the cell sizes are 8.5 μm×12.8 μm, respectively. The gate oxide thickness is 200 Å, and the lightly doped drain (LDD) structure is adopted for the n-channel transistor. A 256-kb full CMOS SRAM utilizing the new technology has achieved a wide operating voltage from 1 V to 7 V and 5 mW (at f=1 MHz & VCC=5 V) and 0.2 mW (at f=1 MHz & VCC=1 V) power dissipation. The address input and data output signals with 100 pF load capacitance of V CC=1 V are shown

A 1 V operating 256-Kbit full CMOS SRAM

A full CMOS six-transistor memory cell was fabricated with single-polysilicon, double-metal technology. The channel lengths of n-channel and p-channel transistors are 0.8 mm and 1.2 mm and the cell sizes are 8.5 mmt12.8 mm, respectively. The gate oxide thickness is 200 A, and the lightly doped drain (LDD) structure is adopted for the n-channel transistor. A 256-kb full CMOS SRAM utilizing the new technology has achieved a wide operating voltage from 1 V to 7 V and 5 mW (at f =1 MHz a V CC=5 V) and 0.2 mW (at f =1 MHz a VCC=1 V) power dissipation. The address input and data output signals with 100 pF load capacitance of V CC=1 V are shown

A 6 ns 1 Mb CMOS SRAM with high-performance sense amplifier

A 1-Mb (256 K*4) SRAM with an access time of 6 ns using a 0.5- mu m CMOS technology is described. Fast access and low power dissipation are achieved by using a new nMOS source-controlled latched sense amplifier and a data output pre-reset circuit that reduces the output transition time.<<ETX>>

4587639 Static semiconductor memory device incorporating redundancy memory cells

In a static semiconductor memory device incorporating redundancy memory cells (CR0, CR1, . . . ), a connecting/disconnecting circuit is linked between a power supply terminal (VCC) and one of bit lines (B0, B0, . . . ), thereby reducing or cutting off a current flowing through a defective memory cell.